| Message ID | 20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com |
|---|---|
| Headers | show |
| Series | spi: amlogic: meson-spicc: Use pinctrl to drive CLK line when idle | expand |
Hi, On Fri, 21 Oct 2022 15:31:24 +0200, Amjad Ouled-Ameur wrote: > Between SPI transactions, all SPI pins are in HiZ state. When using the SS > signal from the SPICC controller it's not an issue because when the > transaction resumes all pins come back to the right state at the same time > as SS. > > The problem is when we use CS as a GPIO. In fact, between the GPIO CS > state change and SPI pins state change from idle, you can have a missing or > spurious clock transition. > > [...] Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.2/arm64-dt) [3/4] arm64: dts: meson-gxl: add SPI pinctrl nodes for CLK https://git.kernel.org/amlogic/c/2ba370bb98b53b7565493083699d82da5ef2cec8 [4/4] arm64: dts: meson-gxbb: add SPI pinctrl nodes for CLK https://git.kernel.org/amlogic/c/ce759829b8fffac891780611b54a6be26a2d5a5f These changes has been applied on the intermediate git tree [1]. The v6.2/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers for inclusion in their intermediate git branches in order to be sent to Linus during the next merge window, or sooner if it's a set of fixes. In the cases of fixes, those will be merged in the current release candidate kernel and as soon they appear on the Linux master branch they will be backported to the previous Stable and Long-Stable kernels [2]. The intermediate git branches are merged daily in the linux-next tree [3], people are encouraged testing these pre-release kernels and report issues on the relevant mailing-lists. If problems are discovered on those changes, please submit a signed-off-by revert patch followed by a corrective changeset. [1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message. Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> --- Changes in v4: - Fixed documentation by defining pinctrl-x. - Link to v3: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com Changes in v3: - Fixed documentation by removing pinctrl states as they are not mandatory. - Link to v2: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com --- Amjad Ouled-Ameur (4): spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states spi: meson-spicc: Use pinctrl to drive CLK line when idle arm64: dts: meson-gxl: add SPI pinctrl nodes for CLK arm64: dts: meson-gxbb: add SPI pinctrl nodes for CLK .../bindings/spi/amlogic,meson-gx-spicc.yaml | 75 ++++++++++++++-------- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 14 ++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 ++++ drivers/spi/spi-meson-spicc.c | 39 ++++++++++- 4 files changed, 113 insertions(+), 29 deletions(-) --- base-commit: e35184f321518acadb681928a016da21a9a20c13 change-id: 20221004-up-aml-fix-spi-c2bb7e78e603 Best regards,