| Message ID | 20230510081121.3463710-1-bigunclemax@gmail.com |
|---|---|
| Headers | show |
| Series | Allwinner R329/D1/R528/T113s SPI support | expand |
On Wed, 10 May 2023 11:11:08 +0300 Maksim Kiselev <bigunclemax@gmail.com> wrote: Hi, > Listed above Allwinner SoCs has two SPI controllers. First is the regular > SPI controller and the second one has additional functionality for > MIPI-DBI Type C. > > Add compatible strings for these controllers > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> thanks for the changes, looks good now and dt-validate passes. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre > --- > .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml > index de36c6a34a0f..fa5260eca531 100644 > --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml > +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml > @@ -19,6 +19,7 @@ properties: > > compatible: > oneOf: > + - const: allwinner,sun50i-r329-spi > - const: allwinner,sun6i-a31-spi > - const: allwinner,sun8i-h3-spi > - items: > @@ -28,6 +29,15 @@ properties: > - allwinner,sun50i-h616-spi > - allwinner,suniv-f1c100s-spi > - const: allwinner,sun8i-h3-spi > + - items: > + - enum: > + - allwinner,sun20i-d1-spi > + - allwinner,sun50i-r329-spi-dbi > + - const: allwinner,sun50i-r329-spi > + - items: > + - const: allwinner,sun20i-d1-spi-dbi > + - const: allwinner,sun50i-r329-spi-dbi > + - const: allwinner,sun50i-r329-spi > > reg: > maxItems: 1
On Wed, 10 May 2023 11:11:10 +0300 Maksim Kiselev <bigunclemax@gmail.com> wrote: > Previously SPI controllers in Allwinner SoCs has a clock divider inside. > However now the clock divider is removed and to set the transfer clock > rate it's only needed to set the SPI module clock to the target value > and configure a proper work mode. > > According to the datasheet there are three work modes: > > | SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock | > |-------------------------|------------|------------|-----------| > | normal sample | 1 | 0 | <= 24 MHz | > | delay half cycle sample | 0 | 0 | <= 40 MHz | > | delay one cycle sample | 0 | 1 | >= 80 MHz | > > Add a quirk for this kind of SPI controllers. > > Co-developed-by: Icenowy Zheng <icenowy@aosc.io> > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Looks good now. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre > --- > drivers/spi/spi-sun6i.c | 91 +++++++++++++++++++++++++++-------------- > 1 file changed, 61 insertions(+), 30 deletions(-) > > diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c > index 01a01cd86db5..e4efab310469 100644 > --- a/drivers/spi/spi-sun6i.c > +++ b/drivers/spi/spi-sun6i.c > @@ -42,7 +42,9 @@ > #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) > #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) > #define SUN6I_TFR_CTL_DHB BIT(8) > +#define SUN6I_TFR_CTL_SDC BIT(11) > #define SUN6I_TFR_CTL_FBS BIT(12) > +#define SUN6I_TFR_CTL_SDM BIT(13) > #define SUN6I_TFR_CTL_XCH BIT(31) > > #define SUN6I_INT_CTL_REG 0x10 > @@ -87,6 +89,7 @@ > > struct sun6i_spi_cfg { > unsigned long fifo_depth; > + bool has_clk_ctl; > }; > > struct sun6i_spi { > @@ -260,7 +263,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, > struct spi_transfer *tfr) > { > struct sun6i_spi *sspi = spi_master_get_devdata(master); > - unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; > + unsigned int div, div_cdr1, div_cdr2, timeout; > unsigned int start, end, tx_time; > unsigned int trig_level; > unsigned int tx_len = 0, rx_len = 0; > @@ -350,39 +353,65 @@ static int sun6i_spi_transfer_one(struct spi_master *master, > > sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); > > - /* Ensure that we have a parent clock fast enough */ > - mclk_rate = clk_get_rate(sspi->mclk); > - if (mclk_rate < (2 * tfr->speed_hz)) { > - clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); > - mclk_rate = clk_get_rate(sspi->mclk); > - } > + if (sspi->cfg->has_clk_ctl) { > + unsigned int mclk_rate = clk_get_rate(sspi->mclk); > > - /* > - * Setup clock divider. > - * > - * We have two choices there. Either we can use the clock > - * divide rate 1, which is calculated thanks to this formula: > - * SPI_CLK = MOD_CLK / (2 ^ cdr) > - * Or we can use CDR2, which is calculated with the formula: > - * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) > - * Wether we use the former or the latter is set through the > - * DRS bit. > - * > - * First try CDR2, and if we can't reach the expected > - * frequency, fall back to CDR1. > - */ > - div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); > - div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); > - if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { > - reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; > - tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); > + /* Ensure that we have a parent clock fast enough */ > + if (mclk_rate < (2 * tfr->speed_hz)) { > + clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); > + mclk_rate = clk_get_rate(sspi->mclk); > + } > + > + /* > + * Setup clock divider. > + * > + * We have two choices there. Either we can use the clock > + * divide rate 1, which is calculated thanks to this formula: > + * SPI_CLK = MOD_CLK / (2 ^ cdr) > + * Or we can use CDR2, which is calculated with the formula: > + * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) > + * Wether we use the former or the latter is set through the > + * DRS bit. > + * > + * First try CDR2, and if we can't reach the expected > + * frequency, fall back to CDR1. > + */ > + div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); > + div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); > + if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { > + reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; > + tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); > + } else { > + div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); > + reg = SUN6I_CLK_CTL_CDR1(div); > + tfr->effective_speed_hz = mclk_rate / (1 << div); > + } > + > + sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); > } else { > - div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); > - reg = SUN6I_CLK_CTL_CDR1(div); > - tfr->effective_speed_hz = mclk_rate / (1 << div); > + clk_set_rate(sspi->mclk, tfr->speed_hz); > + tfr->effective_speed_hz = clk_get_rate(sspi->mclk); > + > + /* > + * Configure work mode. > + * > + * There are three work modes depending on the controller clock > + * frequency: > + * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0 > + * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0 > + * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1 > + */ > + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); > + reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC); > + > + if (tfr->effective_speed_hz <= 24000000) > + reg |= SUN6I_TFR_CTL_SDM; > + else if (tfr->effective_speed_hz >= 80000000) > + reg |= SUN6I_TFR_CTL_SDC; > + > + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); > } > > - sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); > /* Finally enable the bus - doing so before might raise SCK to HIGH */ > reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); > reg |= SUN6I_GBL_CTL_BUS_ENABLE; > @@ -701,10 +730,12 @@ static void sun6i_spi_remove(struct platform_device *pdev) > > static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = { > .fifo_depth = SUN6I_FIFO_DEPTH, > + .has_clk_ctl = true, > }; > > static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { > .fifo_depth = SUN8I_FIFO_DEPTH, > + .has_clk_ctl = true, > }; > > static const struct of_device_id sun6i_spi_match[] = {
Dne sreda, 10. maj 2023 ob 10:11:10 CEST je Maksim Kiselev napisal(a): > Previously SPI controllers in Allwinner SoCs has a clock divider inside. > However now the clock divider is removed and to set the transfer clock > rate it's only needed to set the SPI module clock to the target value > and configure a proper work mode. > > According to the datasheet there are three work modes: > | SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock | > | > |-------------------------|------------|------------|-----------| > | > | normal sample | 1 | 0 | <= 24 MHz | > | delay half cycle sample | 0 | 0 | <= 40 MHz | > | delay one cycle sample | 0 | 1 | >= 80 MHz | > > Add a quirk for this kind of SPI controllers. > > Co-developed-by: Icenowy Zheng <icenowy@aosc.io> > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
Dne sreda, 10. maj 2023 ob 10:11:08 CEST je Maksim Kiselev napisal(a): > Listed above Allwinner SoCs has two SPI controllers. First is the regular > SPI controller and the second one has additional functionality for > MIPI-DBI Type C. > > Add compatible strings for these controllers > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
On Wed, 10 May 2023 11:11:07 +0300, Maksim Kiselev wrote: > v5: > - fixed DT bindings (Allowed three-string compatibility) > > v4: > - fixed SPI sample mode configuration > - sorted DT bindings list > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/5] dt-bindings: spi: sun6i: add DT bindings for Allwinner R329/D1/R528/T113s SPI commit: f603a3f083aeb9438865975c28b27be0afaae0c1 [2/5] spi: sun6i: change OF match data to a struct commit: b00c0d8932f1e7e36570edf0f000c64399e985e0 [3/5] spi: sun6i: add quirk for in-controller clock divider commit: 8e886ac838ef12f6994ed9b13ab87784c4f0bc35 [4/5] spi: sun6i: add support for R329/D1/R528/T113s SPI controllers commit: 046484cb214b43dc4463343e8c49133d9edb5454 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Dne sreda, 10. maj 2023 ob 10:11:12 CEST je Maksim Kiselev napisal(a): > Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have > an optional SPI flash that connects to the SPI0 controller. > > This controller is the same for R329/D1/R528/T113s SoCs and > should be supported by the sun50i-r329-spi driver. > > So let's add its DT nodes. > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> Applied, thanks! Best regards, Jernej
v5: - fixed DT bindings (Allowed three-string compatibility) v4: - fixed SPI sample mode configuration - sorted DT bindings list v3: - fixed effective_speed_hz setup and added SPI sample mode configuration - merged DT bindings for R329 and D1 SPI controllers - added SPI_DBI node to sunxi-d1s-t113.dtsi v2: - added DT bindings and node for D1/T113s Icenowy Zheng (1): spi: sun6i: change OF match data to a struct Icenowy Zheng (1): spi: sun6i: change OF match data to a struct Maksim Kiselev (4): dt-bindings: spi: sun6i: add DT bindings for Allwinner R329/D1/R528/T113s SPI spi: sun6i: add quirk for in-controller clock divider spi: sun6i: add support for R329/D1/R528/T113s SPI controllers riscv: dts: allwinner: d1: Add SPI controllers node .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 10 ++ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 37 +++++ drivers/spi/spi-sun6i.c | 131 ++++++++++++------ 3 files changed, 138 insertions(+), 40 deletions(-)