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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id u6-20020a170903124600b001d71ef6afe0sm10481963plh.103.2024.02.01.01.44.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 01:44:00 -0800 (PST) Received: from hqs-appsw-appswa2.mp600.macronix.com (linux-patcher [172.17.236.35]) by twhmp6px (Postfix) with ESMTPS id B87E280671; Thu, 1 Feb 2024 17:50:00 +0800 (CST) From: Jaime Liao <jaimeliao.tw@gmail.com> To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw Subject: [PATCH v8 0/9] Add octal DTR support for Macronix flash Date: Thu, 1 Feb 2024 17:43:44 +0800 Message-Id: <20240201094353.33281-1-jaimeliao.tw@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: <linux-spi.vger.kernel.org> List-Subscribe: <mailto:linux-spi+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-spi+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
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Add octal DTR support for Macronix flash
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Jaime, You're so close to have these integrated, I see there are no major comments for the patch set. Would you please address the comments and re-submit? I plan to do the PR next Monday. ta
From: JaimeLiao <jaimeliao@mxic.com.tw> Add method for Macronix Octal DTR Eable/Disable. Merge Tudor's patch "Allow specifying the byte order in DTR mode" Add support for Macronix flash v8: Supplement missing S-o-b Remove function spi_nor_is_octal_dtr_swab16 Split IDs by MX25 & MX66 Add dump of capability in debugfs Add dump of params in debugfs Add dump of reult for mtd-utils tests Add SNOR_ID(0xC2) in last of Macronix ID table v7: Add dtr_swab16 judgement to enable/disable Macronix xSPI host controller swap byte feature. v6: Add byte swap support for spi-mxic.c Remove flash name in ID table. v5: Remove manufacturer read id function. For increased readability, separate Flash IDs based on whether it supports RWW feature. v4: Add patch for adding manufacturer read id function. remove patch "hook manufacturer by checking first byte id" v3: Add patch for hook manufacturer by comparing ID 1st byte. Add patches for specifying the byte order in DTR mode by merging Tudor's patch. v2: Following exsting rules to re-create Macronix specify Octal DTR method. change signature to jaimeliao@mxic.com.tw Clear sector size information in flash INFO. JaimeLiao (9): mtd: spi-nor: add Octal DTR support for Macronix flash spi: spi-mem: Allow specifying the byte order in Octal DTR mode mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT spi: mxic: Add support for swapping byte mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature mtd: spi-nor: add support for Macronix Octal flash MX66 series with RWW feature mtd: spi-nor: add support for Macronix Octal flash MX25 series mtd: spi-nor: add support for Macronix Octal flash MX66 series drivers/mtd/spi-nor/core.c | 5 + drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/macronix.c | 169 +++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/sfdp.c | 4 + drivers/mtd/spi-nor/sfdp.h | 1 + drivers/spi/spi-mem.c | 4 + drivers/spi/spi-mxic.c | 17 +++- include/linux/spi/spi-mem.h | 6 ++ 8 files changed, 203 insertions(+), 4 deletions(-)