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[0/3] spi: dw: Auto-detect number of native CS

Message ID 20240215180102.13887-1-fancer.lancer@gmail.com
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Series spi: dw: Auto-detect number of native CS | expand

Message

Serge Semin Feb. 15, 2024, 6 p.m. UTC
The main goal of the short series is to provide a procedure implementing
the auto-detection of the number of native Chip-Select signals supported
by the controller. The suggested algorithm is straightforward. It relies
on the fact that the SER register writable flags reflects the actual
number of available native chip-select signals. So the DW APB/AHB SSI
driver now tests the SER register for having the writable bits,
calculates the number of CS signals based on the number of set flags and
then initializes the num_cs private data field based on that, which then
will be passed to the SPI-core subsystem indicating the number of
supported hardware chip-selects. The implemented procedure will be useful
for the DW SSI device nodes not having the explicitly set "num-cs"
property. In case if the property is specified it will be utilized instead
of the auto-detection procedure.

Besides of that a small cleanup patch is introduced in the head of the
series. It converts the driver to using the BITS_TO_BYTES() macro instead
of the hard-coded DIV_ROUND_UP()-based calculation of the number of
bytes-per-transfer-word.

Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Andy Shevchenko <andy@kernel.org>
Cc: linux-spi@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Serge Semin (3):
  spi: dw: Convert to using BITS_TO_BYTES() macro
  spi: dw: Add a number of native CS auto-detection
  spi: dw: Drop default number of CS setting

 drivers/spi/spi-dw-core.c | 20 ++++++++++++++++----
 drivers/spi/spi-dw-mmio.c |  7 ++-----
 2 files changed, 18 insertions(+), 9 deletions(-)

Comments

Andy Shevchenko Feb. 15, 2024, 7:31 p.m. UTC | #1
On Thu, Feb 15, 2024 at 09:00:47PM +0300, Serge Semin wrote:
> Aside with the FIFO depth and DFS field size it's possible to auto-detect
> a number of native chip-select synthesized in the DW APB/AHB SSI IP-core.
> It can be done just by writing ones to the SER register. The number of
> writable flags in the register is limited by the SSI_NUM_SLAVES IP-core
> synthesize parameter. All the upper flags are read-only and wired to zero.
> Based on that let's add the number of native CS auto-detection procedure
> so the low-level platform drivers wouldn't need to manually set it up
> unless it's required to set a constraint due to platform-specific reasons
> (for instance, due to a hardware bug).

...

> +	/*
> +	 * Try to detect the number of native chip-selects if the platform
> +	 * driver didn't set it up. There can be up to 16 lines configured.
> +	 */
> +	if (!dws->num_cs) {
> +		u32 ser;
> +
> +		dw_writel(dws, DW_SPI_SER, 0xffff);

GENMASK() ?

> +		ser = dw_readl(dws, DW_SPI_SER);
> +		dw_writel(dws, DW_SPI_SER, 0);

Would it actually change the physical line state? If so, we may not do this.

> +		dws->num_cs = hweight16(ser);

Why 16 and not u16 & dw_writew()/readw()?

> +	}

I'm wondering why this can't be the default

	num_cs = ...autodetected...
	device_property_read(..., &num_cs);