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[v1,0/2] Add optional reset control for Cadence SPI

Message ID 20240424051317.2084059-1-jisheng.teoh@starfivetech.com
Headers show
Series Add optional reset control for Cadence SPI | expand

Message

Ji Sheng Teoh April 24, 2024, 5:13 a.m. UTC 
The first patch adds optional reset control to support assertion and
deassertion of reset signal to properly bring the SPI device into an
operating condition.
The second patch documents the optional reset control into dt-bindings.

Ji Sheng Teoh (2):
  spi: spi-cadence: Add optional reset control support
  dt-bindings: spi: spi-cadence: Add optional reset control

 .../devicetree/bindings/spi/spi-cadence.yaml         |  5 +++++
 drivers/spi/spi-cadence.c                            | 12 ++++++++++++
 2 files changed, 17 insertions(+)

Comments

Lars-Peter Clausen April 25, 2024, 1:54 a.m. UTC | #1 
On 4/23/24 22:13, Ji Sheng Teoh wrote:
> Add optional reset control support for spi-cadence to properly bring
> the SPI device into an operating condition.
>
> Signed-off-by: Eng Lee Teh <englee.teh@starfivetech.com>
> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
> ---
>   drivers/spi/spi-cadence.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
> index e5140532071d..41f2f51d39e4 100644
> --- a/drivers/spi/spi-cadence.c
> +++ b/drivers/spi/spi-cadence.c
> @@ -111,6 +111,7 @@
>    * @dev_busy:		Device busy flag
>    * @is_decoded_cs:	Flag for decoder property set or not
>    * @tx_fifo_depth:	Depth of the TX FIFO
> + * @rstc:		Optional reset control for SPI controller
>    */
>   struct cdns_spi {
>   	void __iomem *regs;
> @@ -125,6 +126,7 @@ struct cdns_spi {
>   	u8 dev_busy;
>   	u32 is_decoded_cs;
>   	unsigned int tx_fifo_depth;
> +	struct reset_control *rstc;
>   };
>   
>   /* Macros for the SPI controller read/write */
> @@ -588,6 +590,16 @@ static int cdns_spi_probe(struct platform_device *pdev)
>   		goto remove_ctlr;
>   	}
>   
> +	xspi->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);

The cadence SPI core has 3 different resets signals. Maybe use a name 
for the reset to make it clear which reset this is referring to.

> +	if (IS_ERR(xspi->rstc)) {
> +		ret = PTR_ERR(xspi->rstc);
> +		dev_err(&pdev->dev, "Cannot get SPI reset.\n");
> +		goto remove_ctlr;
> +	}
> +
> +	reset_control_assert(xspi->rstc);
> +	reset_control_deassert(xspi->rstc);
> +
>   	if (!spi_controller_is_target(ctlr)) {
>   		xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk");
>   		if (IS_ERR(xspi->ref_clk)) {