| Message ID | 20250428-adi-main-v1-0-4b8a1b88a212@baylibre.com |
|---|---|
| Headers | show |
| Series | spi: axi-spi-engine: offload instruction optimization | expand |
On Mon, 28 Apr 2025 15:58:55 -0500, David Lechner wrote: > In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK > using the SPI offload feature of the AXI SPI Engine, we need to shave > off some time that is spent executing unnecessary instructions. There > are a few one-time setup instructions that can be moved so that they > execute only once when the SPI offload trigger is enabled rather than > repeating each time the offload is triggered. Additionally, a recent > change to the IP block allows dropping the SYNC instruction completely. > With these changes, we are left with only the 3 instructions that are > needed to to assert CS, transfer the data, and deassert CS. This makes > 3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is comfortably within the > available time period. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/4] spi: axi-spi-engine: wait for completion in setup commit: 1d0ee0c9df31c9fd1e4f8d7e2464e36fbf6e3f75 [2/4] spi: axi-spi-engine: don't repeat mode config for offload commit: 8fc13b822c74a46587c0d8aae4ea0820b6bdb933 [3/4] spi: axi-spi-engine: optimize bits_per_word for offload commit: 087591c9e4fde86fe2971c34a2745c208103248e [4/4] spi: axi-spi-engine: omit SYNC from offload instructions commit: e6702c44c2adb28b62f81de498e9b1e4562ce660 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK using the SPI offload feature of the AXI SPI Engine, we need to shave off some time that is spent executing unnecessary instructions. There are a few one-time setup instructions that can be moved so that they execute only once when the SPI offload trigger is enabled rather than repeating each time the offload is triggered. Additionally, a recent change to the IP block allows dropping the SYNC instruction completely. With these changes, we are left with only the 3 instructions that are needed to to assert CS, transfer the data, and deassert CS. This makes 3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is comfortably within the available time period. Signed-off-by: David Lechner <dlechner@baylibre.com> --- David Lechner (4): spi: axi-spi-engine: wait for completion in setup spi: axi-spi-engine: don't repeat mode config for offload spi: axi-spi-engine: optimize bits_per_word for offload spi: axi-spi-engine: omit SYNC from offload instructions drivers/spi/spi-axi-spi-engine.c | 91 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 85 insertions(+), 6 deletions(-) --- base-commit: aba9c2fee9598d797034ffd289b0da770d9119e8 change-id: 20250331-adi-main-46863acfc540 Best regards,