From patchwork Tue Nov 22 08:25:09 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 5264 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C802A23E0C for ; Tue, 22 Nov 2011 08:25:25 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 85B58A18552 for ; Tue, 22 Nov 2011 08:25:25 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id a26so135351faa.11 for ; Tue, 22 Nov 2011 00:25:25 -0800 (PST) Received: by 10.152.162.10 with SMTP id xw10mr11065563lab.12.1321950325309; Tue, 22 Nov 2011 00:25:25 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs166944lal; Tue, 22 Nov 2011 00:25:24 -0800 (PST) Received: by 10.213.21.197 with SMTP id k5mr1014097ebb.56.1321950323335; Tue, 22 Nov 2011 00:25:23 -0800 (PST) Received: from eu1sys200aog118.obsmtp.com (eu1sys200aog118.obsmtp.com. [207.126.144.145]) by mx.google.com with SMTP id q28si2984132eea.48.2011.11.22.00.25.14 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 00:25:23 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.145; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKTstcaWWX2ffqDFbxGMQiOrvfgg/WRJob@postini.com; Tue, 22 Nov 2011 08:25:23 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2C0EBB8; Tue, 22 Nov 2011 08:25:13 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C6B38195E; Tue, 22 Nov 2011 08:25:12 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 05D9324C2F3; Tue, 22 Nov 2011 09:25:08 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 22 Nov 2011 09:25:12 +0100 From: Linus Walleij To: Grant Likely , Cc: , Viresh Kumar , Virupax Sadashivpetimath , Linus Walleij Subject: [PATCH 5/7] spi/pl022: disable the PL022 block when unused Date: Tue, 22 Nov 2011 09:25:09 +0100 Message-ID: <1321950309-4816-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Virupax Sadashivpetimath Make sure we clear the enable bit when the block is not used. This will save some energy in certain hardware versions. Reviewed-by: Viresh Kumar Signed-off-by: Virupax Sadashivpetimath Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Move this patch after the movement of disabling code to workqueue at Viresh:s request. - Add Vireshs Reviewed-by --- drivers/spi/spi-pl022.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index 8cdf052..82a929f 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -1513,6 +1513,9 @@ static void pump_messages(struct work_struct *work) spin_lock_irqsave(&pl022->queue_lock, flags); if (list_empty(&pl022->queue) || !pl022->running) { if (pl022->busy) { + /* nothing more to do - disable spi/ssp and power off */ + writew((readw(SSP_CR1(pl022->virtbase)) & + (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); pm_runtime_put(&pl022->adev->dev); } pl022->busy = false;