| Message ID | 20220216014028.8123-7-jon.lin@rock-chips.com |
|---|---|
| State | Accepted |
| Commit | 2fcdde56c44fe1cd13ce328128f509bbda2cdb41 |
| Headers | show |
| Series | New support and problem adjustment of SPI rockchip | expand |
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 8b4d56ee2193..cdc16eecaf6b 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -278,8 +278,9 @@ static void rockchip_spi_handle_err(struct spi_controller *ctlr, */ spi_enable_chip(rs, false); - /* make sure all interrupts are masked */ + /* make sure all interrupts are masked and status cleared */ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); + writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); if (atomic_read(&rs->state) & TXDMA) dmaengine_terminate_async(ctlr->dma_tx);
The interrupt status bit of the previous error data transmition will affect the next operation and cause continuous SPI transmission failure. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> --- Changes in v3: None Changes in v2: None Changes in v1: None drivers/spi/spi-rockchip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)