| Message ID | 20241028105413.146510-1-francesco@dolcini.it |
|---|---|
| Headers | show |
| Series | USB: xhci: add support for PWRON polarity invert (TI TUSB73x0) | expand |
On Mon, Oct 28, 2024 at 11:54:12AM +0100, Francesco Dolcini wrote: > From: Parth Pancholi <parth.pancholi@toradex.com> > > Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI > host controller. The controller supports software configuration > through PCIe registers, such as controlling the PWRONx polarity > via the USB control register (E0h). > > Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> > --- > v4: > - add $ref: usb-xhci.yaml > - description: wrap to 80 columns, add that the two variants use the > same device ID > - revise the example, based on comment from Rob and taking > marvell,prestera.yaml as an example (this binding was reviewed and > amended by Rob in the past). > v3: use lowercase hex in compatible > v2: rename property to ti,tusb7320-pwron-active-high and change type to flag > --- > .../bindings/usb/ti,tusb73x0-pci.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > > diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > new file mode 100644 > index 000000000000..e98a2e0bfcbb > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) > + > +maintainers: > + - Francesco Dolcini <francesco.dolcini@toradex.com> > + > +description: > + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. > + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up > + to four downstream ports, both variants share the same PCI device ID. > + > +properties: > + compatible: > + const: pci104c,8241 > + > + reg: > + maxItems: 1 > + > + ti,tusb7320-pwron-active-high: Drop tusb7320. There is never device name in property name, because it is redundant and makes it completely not-reusable. > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Configure the polarity of the PWRONx# signals. When this is present, the > + PWRONx# pins are active high and their internal pull-down resistors are > + disabled. When this is absent, the PWRONx# pins are active low (default) > + and their internal pull-down resistors are enabled. Best regards, Krzysztof
Hello Krzysztof, On Tue, Oct 29, 2024 at 08:08:09AM +0100, Krzysztof Kozlowski wrote: > On Mon, Oct 28, 2024 at 11:54:12AM +0100, Francesco Dolcini wrote: > > From: Parth Pancholi <parth.pancholi@toradex.com> > > > > Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI > > host controller. The controller supports software configuration > > through PCIe registers, such as controlling the PWRONx polarity > > via the USB control register (E0h). > > > > Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf > > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> ... > > + ti,tusb7320-pwron-active-high: > > Drop tusb7320. There is never device name in property name, because it > is redundant and makes it completely not-reusable. Whoops :/ Rob already wrote this in the previous version and I forgot about it. Thanks!
From: Francesco Dolcini <francesco.dolcini@toradex.com> The TUSB73x0 is a USB 3.0 xHCI Host Controller Hub using a PCIe x1 Gen2 interface. The TUSB7320 supports up to two downstream ports, and the TUSB7340 supports up to four. It includes a feature to configure the polarity of the PWRONx# signals, which are used to control other peripherals. In some systems, the default polarity needs to be inverted, which is supported by the hardware through software configuration. This patch series introduces TUSB73x0 PCIe device tree bindings and modifies the USB XHCI PCI driver to handle PWRONx# polarity via a device tree property. TUSB73x0 datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf v4: - DT binding: revise example, add $ref: usb-xhci.yaml v3: https://lore.kernel.org/all/20241018105505.28005-1-francesco@dolcini.it/ - Correct the compatible string as "pci104c,8241" (uppercase hex to lowercase) v2: https://lore.kernel.org/all/20241007093205.27130-1-francesco@dolcini.it/ - Change the property type from bool to flag - Rename the property as ti,tusb7320-pwron-active-high v1: https://lore.kernel.org/all/20241004124521.53442-1-francesco@dolcini.it/ Parth Pancholi (2): dt-bindings: usb: add TUSB73x0 PCIe USB: xhci: add support for PWRON active high .../bindings/usb/ti,tusb73x0-pci.yaml | 55 +++++++++++++++++++ drivers/usb/host/xhci-pci.c | 3 + 2 files changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml