From patchwork Thu Feb 20 14:33:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 867079 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01D3E28EA; Thu, 20 Feb 2025 14:34:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740062051; cv=none; b=ZHfEHlm8Q2rE93SIJvgb0b746PmpM6jODgrq7su2kdzqfIm8yyqy7kEuaAbJatFiy2GIjsHLpJCKgeCwdH94HLEg8h+Ve+g7uXhefueg9NCTipmCHBoQAsbvOy5Autwsj0wzwUGVIV3FnkyMCXeAb75aakuPhq403+Lnv0cKvHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740062051; c=relaxed/simple; bh=m6EWfbWqhNEv4YKFx0ZpQOhi4YTb8/Jvu+gSnhzL06o=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=X+vwek+xqzSjh8x+Fhb9Ny0qP2J6ojvdr+QLkSBn5QUy3lhIt2tfxBNP+KSx/xQjgOoVWj17DXB7UE1rt4t5ECUBUGy7wEeWi7Q6HJbt3UPu3qW6pFH9qoF/GYfIT3MkItsVBqiEAOlLbe452yh8K23OIi22FgMHmuxQFk0+OFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=f4RAmhu/; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="f4RAmhu/" X-UUID: bc2be53cef9711efaae1fd9735fae912-20250220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=LDoKuVQJ2EJOVY+wYzqwfD5konrYdOHBBkVXoeUifQw=; b=f4RAmhu/w6/pM6SmBq+YEJ/jnXtKPu6b3KWxFazEGiJp/wRKHjVHFp7CtT65o6IEXJryzvBl1tGC2nEi0aHqqHOKUNi7eA9u8XSKRK/jLWd179tXUUv2WxWIfF4lAag1pQ1lkJRxrV43FGnNLKJ/P+FQlXcGVULj4RKLV/9XfWk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46, REQID:4f846745-ece4-494e-87af-2d53eb40ed44, IP:0, U RL:0,TC:0,Content:0,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:60aa074, CLOUDID:0d925aa4-5c06-4e72-8298-91cabc9efadf, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0|50,EDM:1|19,IP: nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,L ES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: bc2be53cef9711efaae1fd9735fae912-20250220 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1645261871; Thu, 20 Feb 2025 22:34:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Thu, 20 Feb 2025 22:34:03 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Thu, 20 Feb 2025 22:34:03 +0800 From: Macpaul Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , , , , , Alexandre Mergnat CC: Bear Wang , Pablo Sun , Macpaul Lin , Macpaul Lin , , , Chris-qj chen , Fabien Parent , Yow-Shin Liou , Simon Sun Subject: [PATCH v4 1/2] arm64: dts: mediatek: mt8395-genio-1200-evk: add support for TCPC port Date: Thu, 20 Feb 2025 22:33:53 +0800 Message-ID: <20250220143354.2532448-1-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Fabien Parent Enable USB Type-C support on MediaTek MT8395 Genio 1200 EVK by adding configuration for TCPC Port, USB-C connector, and related settings. Configure dual role switch capability, set up PD (Power Delivery) profiles, and establish endpoints for SS (SuperSpeed) and HS (HighSpeed) USB. Update pinctrl configurations for U3 P0 VBus default pins and set dr_mode to "otg" for OTG (On-The-Go) mode operation. Signed-off-by: Fabien Parent Signed-off-by: Yow-Shin Liou Signed-off-by: Simon Sun Signed-off-by: Macpaul Lin --- .../dts/mediatek/mt8395-genio-1200-evk.dts | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) Changes for v2: - Drop the no need '1/2' DT Schema update patch in the 1st version. - Fix indent for 'ports' node, it should under the 'connector' node. - Correct the index for 'port@0' and 'port@1' node. Changes for v3: - Correct the order between new added nodes. Changes for v4: - Reorder for property 'op-sink-microwatt'. - Fix indentation for 'source-pdos' and 'sink-pdos' nodes. - Correct node 'pin-cmd-dat' with 'pins-vbus'. - Add both Highspeed and Superspeed ports to ssusb0 port. - Set 'role-switch-default-mode' = "peripheral" for ssusb0 port. - Rename endpoint of USB data port to 'mtu3_hs0_role_sw' and 'mtu3_ss0_role_sw'. diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index 1ef6262b65c9..ca039c8e4c71 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -330,6 +330,47 @@ mt6360_ldo7: ldo7 { regulator-always-on; }; }; + + tcpc { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + + source-pdos = ; + sink-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs0_role_sw>; + }; + }; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&mtu3_ss0_role_sw>; + }; + }; + }; + }; + }; }; }; @@ -755,6 +796,13 @@ pins-reset { }; }; + u3_p0_vbus: u3-p0-vbus-default-pins { + pins-vbus { + pinmux = ; + input-enable; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = , @@ -885,8 +933,32 @@ &ufsphy { }; &ssusb0 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&u3_p0_vbus>; + role-switch-default-mode = "peripheral"; + usb-role-switch; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mtu3_hs0_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; + + port@1 { + reg = <1>; + mtu3_ss0_role_sw: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; }; &ssusb2 {