| Message ID | 20170812184318.10144-1-linus.walleij@linaro.org |
|---|---|
| Headers | show |
| Series | watchdog: Consolidate FTWDT010 derivatives | expand |
Hi Linus, On Sun, Aug 13, 2017 at 4:13 AM, Linus Walleij <linus.walleij@linaro.org> wrote: > The MOXA ART and Aspeed watchdogs are clearly based on the > Faraday Technology FTWDT010 IP block. They have a similar register interface, but I'm told they are not the same IP. We've got some patches on the list that add some extra registers to the driver for the ast2500. If we decide to merge the drivers, that support will need to be included. Andrew was working on that, I'll let him follow up on the details. > This series consolidates the drivers into one by extending > the Gemini driver to be as generic as possible, renaming it > to ftwdt010_wdt and merging the two other drivers into it. > > As similar approach was used for the FTTMR010 driver in the > past. > > The series ends with two patches that will be applied to > the ARM SoC tree to fix up the PCLK annotations, but these > are not needed to make the consolidation, patches 1-9 can > be applied directly to the watchdog tree to perform the > consolidation. The clock isn't called PCLK in the Aspeed documentation (similarly for the timer, but I was too slow to speak up in that case). I'm trying to find some time to write a proper clock driver so it's clear how the clocks are set out in the Aspeed. Cheers, Joel -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, 2017-08-14 at 10:54 +0930, Joel Stanley wrote: > Hi Linus, > > On Sun, Aug 13, 2017 at 4:13 AM, Linus Walleij <linus.walleij@linaro.org> wrote: > > The MOXA ART and Aspeed watchdogs are clearly based on the > > Faraday Technology FTWDT010 IP block. > > They have a similar register interface, but I'm told they are not the same IP. > > We've got some patches on the list that add some extra registers to > the driver for the ast2500. If we decide to merge the drivers, that > support will need to be included. > > Andrew was working on that, I'll let him follow up on the details. There are two series on the lists expanding driver support for the Aspeed watchdog, one from Chris Bostic and another from myself: 1. [PATCH v5 0/2] Add ASPEED watchdog device tree properties: https://lkml.org/lkml/2017/7/17/777 2. [PATCH 0/2] watchdog: aspeed: External reset signal properties: https://www.spinics.net/lists/kernel/msg2570666.html I don't have the datasheets for either the Moxa or Faraday SoCs, so I can't assess how the support I've added for the external pulse properties on Aspeed hardware impacts/is impacted by the merge. Chris' changes on the otherhand look like they could be generalised. At least, the vendor prefix on the devicetree properties he defined could perhaps be changed from aspeed to faraday. Cheers, Andrew PS: Patch 10/11 failed to apply for me against several trees, failing on the hunk for arch/arm/boot/dts/gemini.dtsi. Is there an unmentioned dependency? > > > This series consolidates the drivers into one by extending > > the Gemini driver to be as generic as possible, renaming it > > to ftwdt010_wdt and merging the two other drivers into it. > > > > As similar approach was used for the FTTMR010 driver in the > > past. > > > > The series ends with two patches that will be applied to > > the ARM SoC tree to fix up the PCLK annotations, but these > > are not needed to make the consolidation, patches 1-9 can > > be applied directly to the watchdog tree to perform the > > consolidation. > > The clock isn't called PCLK in the Aspeed documentation (similarly for > the timer, but I was too slow to speak up in that case). > > I'm trying to find some time to write a proper clock driver so it's > clear how the clocks are set out in the Aspeed. > > Cheers, > > Joel
On Mon, Aug 14, 2017 at 3:24 AM, Joel Stanley <joel@jms.id.au> wrote: > On Sun, Aug 13, 2017 at 4:13 AM, Linus Walleij <linus.walleij@linaro.org> wrote: >> The MOXA ART and Aspeed watchdogs are clearly based on the >> Faraday Technology FTWDT010 IP block. > > They have a similar register interface, but I'm told they are not the same IP. They are too similar to not be related somehow. I guess it is one of those Shanzhai-mindset things where IP VHDL or Verilog code is being copied around at silicon foundries in Asia and turn up in different chips "independently" of each other. It doesn't really matter if they "are" the same (as in: silicon vendor admits that they are), if it walks like a duck, act and talks like a duck, it is a duck. And we use the same driver. > We've got some patches on the list that add some extra registers to > the driver for the ast2500. If we decide to merge the drivers, that > support will need to be included. Hm I was not aware, need to read up on it. > Andrew was working on that, I'll let him follow up on the details. > > The clock isn't called PCLK in the Aspeed documentation (similarly for > the timer, but I was too slow to speak up in that case). "PCLK" is just short for "peripheral block", just like other such shorthands like "APB" (AMBA peripheral bridge clock). It's a generic term. Preferrably it should use the name from the IP vendor, but when in conflict about names, it's too much trouble to use different names IMO so I think "PCLK" is just fine. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Aug 14, 2017 at 5:08 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > There are two series on the lists expanding driver support for the Aspeed > watchdog, one from Chris Bostic and another from myself: > > 1. [PATCH v5 0/2] Add ASPEED watchdog device tree properties: > > https://lkml.org/lkml/2017/7/17/777 Looks all right. The SoC vs whole chip reset signal big is an Aspeed-specific extension AFAICT. > > 2. [PATCH 0/2] watchdog: aspeed: External reset signal properties: > > https://www.spinics.net/lists/kernel/msg2570666.html The external reset exists also in the Faraday FTWDT010 block, in the same bit. (No coincidence...) but neither the Gemini or the MOXA ART is using it as far as I know. > I don't have the datasheets for either the Moxa or Faraday SoCs, so I can't > assess how the support I've added for the external pulse properties on Aspeed > hardware impacts/is impacted by the merge. It's no big deal, I can rewrite the patches in the end of the series on top of that stuff also adding this functionality. > Chris' changes on the otherhand look > like they could be generalised. At least, the vendor prefix on the devicetree > properties he defined could perhaps be changed from aspeed to faraday. The "aspeed,reset-type" is fine since it is Aspeed-only. External reset is part of the Faraday IP block so it should be "faraday,external-reset-signal" or so. I will try to see if I can find the patches and comment directly. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Sat, Aug 12, 2017 at 8:43 PM, Linus Walleij <linus.walleij@linaro.org> wrote: > The MOXA ART and Aspeed watchdogs are clearly based on the > Faraday Technology FTWDT010 IP block. Wim/Guenther: it is perfectly fine to just stop merging the series after the say top 3 or top 4 ones etc. The do not need to be applied on an all-or-nothing basis. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html