| Message ID | 20200803071501.30634-5-crystal.guo@mediatek.com |
|---|---|
| State | New |
| Headers | show |
| Series | watchdog: mt8192: add wdt support | expand |
On 8/3/20 12:15 AM, Crystal Guo wrote: > add toprgu reset-controller head file for MT8192 platform > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Guenter Roeck <linux@roeck-us.net> > --- > .../reset-controller/mt8192-resets.h | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h > > diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h > new file mode 100644 > index 000000000000..84fee34f1c32 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt8192-resets.h > @@ -0,0 +1,30 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2020 MediaTek Inc. > + * Author: Yong Liang <yong.liang@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 > + > +#define MT8183_TOPRGU_MM_SW_RST 1 > +#define MT8183_TOPRGU_MFG_SW_RST 2 > +#define MT8183_TOPRGU_VENC_SW_RST 3 > +#define MT8183_TOPRGU_VDEC_SW_RST 4 > +#define MT8183_TOPRGU_IMG_SW_RST 5 > +#define MT8183_TOPRGU_MD_SW_RST 7 > +#define MT8183_TOPRGU_CONN_SW_RST 9 > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 > +#define MT8183_TOPRGU_IPU0_SW_RST 14 > +#define MT8183_TOPRGU_IPU1_SW_RST 15 > +#define MT8183_TOPRGU_AUDIO_SW_RST 17 > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 > +#define MT8192_TOPRGU_MJC_SW_RST 19 > +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 > +#define MT8192_TOPRGU_C2K_SW_RST 21 > +#define MT8192_TOPRGU_PERI_SW_RST 22 > +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 > + > +#define MT8192_TOPRGU_SW_RST_NUM 23 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ >
diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h new file mode 100644 index 000000000000..84fee34f1c32 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang <yong.liang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */