From patchwork Tue Mar 16 11:14:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 403746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DABA2C41518 for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B64D465023 for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237228AbhCPLQO (ORCPT ); Tue, 16 Mar 2021 07:16:14 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48912 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237118AbhCPLP0 (ORCPT ); Tue, 16 Mar 2021 07:15:26 -0400 X-UUID: b8b8bb1b26394cfa838bb4501282a019-20210316 X-UUID: b8b8bb1b26394cfa838bb4501282a019-20210316 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1381749629; Tue, 16 Mar 2021 19:15:21 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:19 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 02/10] dt-bindings: serial: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:35 +0800 Message-ID: <20210316111443.3332-3-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 710D83FF007C2822D4FF14E9AA594A7B428033586ACDF8B86D3933F89E6055C62000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This commit adds dt-binding documentation of uart for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 647b5aee86f3..64c4fb59acd1 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -20,6 +20,7 @@ Required properties: * "mediatek,mt8173-uart" for MT8173 compatible UARTS * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS + * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS * "mediatek,mt8516-uart" for MT8516 compatible UARTS * "mediatek,mt6577-uart" for MT6577 and all of the above