From patchwork Thu Sep 2 05:33:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: P Praneesh X-Patchwork-Id: 506927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28104C4320E for ; Thu, 2 Sep 2021 05:35:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10EB4610C8 for ; Thu, 2 Sep 2021 05:35:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232523AbhIBFgM (ORCPT ); Thu, 2 Sep 2021 01:36:12 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:56644 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232414AbhIBFgM (ORCPT ); Thu, 2 Sep 2021 01:36:12 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1630560914; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=VnFXLKaHfg9HscphaIEFzb3LbjIEFwTs+2hqyPkGKcA=; b=UO3H3Yoxa/ycNGoqKK4ZsUNT2wDvBIoJSB4oJ9/YJfaNDV6Q+tWIfBCOHMJx8uGWpZ9H0s4z fpsrMTZKrbpGjJ2LcwMopVBNJDTgOqdhUPFOiHwl8Aci4KyfrxjsIMOpnDum9EW2c3vwz8H2 9X0n5gafSAi6rXmPyN/avD5Gi3o= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI3YTAwOSIsICJsaW51eC13aXJlbGVzc0B2Z2VyLmtlcm5lbC5vcmciLCAiYmU5ZTRhIl0= Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-east-1.postgun.com with SMTP id 61306286e0fcecca1999dcb0 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 02 Sep 2021 05:35:02 GMT Sender: ppranees=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9EC06C43619; Thu, 2 Sep 2021 05:35:01 +0000 (UTC) Received: from ppranees-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ppranees) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0C926C43460; Thu, 2 Sep 2021 05:34:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 0C926C43460 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org From: P Praneesh To: kvalo@codeaurora.org Cc: ath11k@lists.infradead.org, linux-wireless@vger.kernel.org, P Praneesh , Sriram R , Jouni Malinen Subject: [PATCH v3 08/12] ath11k: allocate HAL_WBM2SW_RELEASE ring from cacheable memory Date: Thu, 2 Sep 2021 11:03:36 +0530 Message-Id: <1630560820-21905-9-git-send-email-ppranees@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1630560820-21905-1-git-send-email-ppranees@codeaurora.org> References: <1630560820-21905-1-git-send-email-ppranees@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Similar to REO destination ring, also allocate HAL_WBM2SW_RELEASE from cacheable memory so that descriptors could be prefetched during tx completion handling. Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1 v2 Co-developed-by: Sriram R Signed-off-by: Sriram R Signed-off-by: Jouni Malinen Signed-off-by: P Praneesh --- drivers/net/wireless/ath/ath11k/dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/ath/ath11k/dp.c b/drivers/net/wireless/ath/ath11k/dp.c index 943d0a7..0278ff6 100644 --- a/drivers/net/wireless/ath/ath11k/dp.c +++ b/drivers/net/wireless/ath/ath11k/dp.c @@ -239,6 +239,7 @@ int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, /* Allocate the reo dst and tx completion rings from cacheable memory */ switch (type) { case HAL_REO_DST: + case HAL_WBM2SW_RELEASE: cached = true; break; default: