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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c35sm13214789pgl.72.2019.08.26.12.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 12:46:06 -0700 (PDT) From: Mathieu Poirier To: suzuki.poulose@arm.com, leo.yan@linaro.org, mike.leach@arm.com Cc: yabinc@google.com, alexander.shishkin@linux.intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] coresight: Add barrier packet when moving offset forward Date: Mon, 26 Aug 2019 13:46:02 -0600 Message-Id: <20190826194605.3791-1-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This set builds on top of an original patch by Yabin Cui[1] that deals with cases where the ETR buffer it bigger than the space available in the perf ring buffer. The work herein complements Yabin's by inserting barrier packets after the head of the memory buffer has been moved forward in order for the trace decoder to still synchronise with the trace stream. Applies cleanly to the coresight next branch. Thanks, Mathieu [1]. https://lkml.org/lkml/2019/8/14/1336 New to V2: - Added Yabin's Tested-by. - Addressed Leo's comment about extending the solution to the sysfs interface. - Split the work in 3 patches rather than 2. Mathieu Poirier (3): coresight: tmc: Make memory width mask computation into a function coresight: tmc-etr: Decouple buffer sync and barrier packet insertion coresight: tmc-etr: Add barrier packets when moving offset forward .../hwtracing/coresight/coresight-tmc-etf.c | 23 +-------- .../hwtracing/coresight/coresight-tmc-etr.c | 47 ++++++++++++++----- drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 4 files changed, 67 insertions(+), 32 deletions(-) -- 2.17.1