From patchwork Tue Jul 19 13:16:56 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 2755 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id AB60523F41 for ; Tue, 19 Jul 2011 13:05:25 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id 6C630A183C1 for ; Tue, 19 Jul 2011 13:05:25 +0000 (UTC) Received: by qwb8 with SMTP id 8so2883918qwb.11 for ; Tue, 19 Jul 2011 06:05:24 -0700 (PDT) Received: by 10.229.68.200 with SMTP id w8mr6310680qci.114.1311080724704; Tue, 19 Jul 2011 06:05:24 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.217.78 with SMTP id hl14cs84020qcb; Tue, 19 Jul 2011 06:05:24 -0700 (PDT) Received: by 10.42.161.4 with SMTP id r4mr8179496icx.496.1311080723827; Tue, 19 Jul 2011 06:05:23 -0700 (PDT) Received: from mail-iw0-f178.google.com (mail-iw0-f178.google.com [209.85.214.178]) by mx.google.com with ESMTPS id bt10si14896627icb.51.2011.07.19.06.05.23 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 19 Jul 2011 06:05:23 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=209.85.214.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: by iwc10 with SMTP id 10so4487598iwc.37 for ; Tue, 19 Jul 2011 06:05:23 -0700 (PDT) Received: by 10.42.168.70 with SMTP id v6mr8760884icy.243.1311080723218; Tue, 19 Jul 2011 06:05:23 -0700 (PDT) Received: from localhost.localdomain ([114.216.156.94]) by mx.google.com with ESMTPS id h6sm506514icy.13.2011.07.19.06.04.56 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 19 Jul 2011 06:05:22 -0700 (PDT) From: Shawn Guo To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Grant Likely , patches@linaro.org, Shawn Guo Subject: [PATCH v2] gpio/mxc/mxs: fix build error introduced by the irq_gc_ack() renaming Date: Tue, 19 Jul 2011 21:16:56 +0800 Message-Id: <1311081416-1251-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1311046444-25423-1-git-send-email-shawn.guo@linaro.org> References: <1311046444-25423-1-git-send-email-shawn.guo@linaro.org> The following commit renames irq_gc_ack() to irq_gc_ack_set_bit(), and makes gpio-mxc and gpio-mxs fail to build. 659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5 genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd) The patch fixed a couple of typo of comma to semicolon. Signed-off-by: Shawn Guo --- Changes since v1: * Fix a couple of typo of comma to semicolon drivers/gpio/gpio-mxc.c | 4 ++-- drivers/gpio/gpio-mxs.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 89fda58..4340aca 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -297,11 +297,11 @@ static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port) gc->private = port; ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack, + ct->chip.irq_ack = irq_gc_ack_set_bit; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_set_type = gpio_set_irq_type; - ct->chip.irq_set_wake = gpio_set_wake_irq, + ct->chip.irq_set_wake = gpio_set_wake_irq; ct->regs.ack = GPIO_ISR; ct->regs.mask = GPIO_IMR; diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c index d8cafba..af55a85 100644 --- a/drivers/gpio/gpio-mxs.c +++ b/drivers/gpio/gpio-mxs.c @@ -156,11 +156,11 @@ static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port) gc->private = port; ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack, + ct->chip.irq_ack = irq_gc_ack_set_bit; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_set_type = mxs_gpio_set_irq_type; - ct->chip.irq_set_wake = mxs_gpio_set_wake_irq, + ct->chip.irq_set_wake = mxs_gpio_set_wake_irq; ct->regs.ack = PINCTRL_IRQSTAT(port->id) + MXS_CLR; ct->regs.mask = PINCTRL_IRQEN(port->id);