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[82.125.33.71]) by mx.google.com with ESMTPSA id es9sm1112100wjd.1.2014.07.23.03.54.13 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 23 Jul 2014 03:54:13 -0700 (PDT) From: Daniel Lezcano To: linux-kernel@vger.kernel.org Subject: [PATCH 06/25] clocksource: sh_mtu2: Replace global spinlock with a per-device spinlock Date: Wed, 23 Jul 2014 12:53:48 +0200 Message-Id: <1406112847-26275-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1406112847-26275-1-git-send-email-daniel.lezcano@linaro.org> References: <53CF93B2.6040903@linaro.org> <1406112847-26275-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Laurent Pinchart The global spinlock is used to protect the shared start/stop register. Now that all MTU2 channels are handled by a single device instance, use a per-device spinlock. Signed-off-by: Laurent Pinchart Tested-by: Wolfram Sang --- drivers/clocksource/sh_mtu2.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c index 0342e4a..b0c229f 100644 --- a/drivers/clocksource/sh_mtu2.c +++ b/drivers/clocksource/sh_mtu2.c @@ -47,14 +47,14 @@ struct sh_mtu2_device { void __iomem *mapbase; struct clk *clk; + raw_spinlock_t lock; /* Protect the shared registers */ + struct sh_mtu2_channel *channels; unsigned int num_channels; bool has_clockevent; }; -static DEFINE_RAW_SPINLOCK(sh_mtu2_lock); - #define TSTR -1 /* shared register */ #define TCR 0 /* channel register */ #define TMDR 1 /* channel register */ @@ -192,7 +192,7 @@ static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) unsigned long flags, value; /* start stop register shared by multiple timer channels */ - raw_spin_lock_irqsave(&sh_mtu2_lock, flags); + raw_spin_lock_irqsave(&ch->mtu->lock, flags); value = sh_mtu2_read(ch, TSTR); if (start) @@ -201,7 +201,7 @@ static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) value &= ~(1 << ch->index); sh_mtu2_write(ch, TSTR, value); - raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags); + raw_spin_unlock_irqrestore(&ch->mtu->lock, flags); } static int sh_mtu2_enable(struct sh_mtu2_channel *ch) @@ -402,6 +402,8 @@ static int sh_mtu2_setup(struct sh_mtu2_device *mtu, mtu->pdev = pdev; + raw_spin_lock_init(&mtu->lock); + /* Get hold of clock. */ mtu->clk = clk_get(&mtu->pdev->dev, "fck"); if (IS_ERR(mtu->clk)) {