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[109.190.224.135]) by mx.google.com with ESMTPSA id k1sm7481817wjn.9.2015.03.26.02.27.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Mar 2015 02:27:16 -0700 (PDT) From: Daniel Lezcano To: mingo@kernel.org, tglx@linutronix.de Cc: maxime.ripard@free-electrons.com, richard@nod.at, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] clocksource: sun5i: Fix cpufreq interaction with sched_clock Date: Thu, 26 Mar 2015 10:27:09 +0100 Message-Id: <1427362029-6511-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427362029-6511-1-git-send-email-daniel.lezcano@linaro.org> References: <5513D019.3050503@free.fr> <1427362029-6511-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Maxime Ripard The sched_clock we use on some system is this timer, and since we started using cpufreq, the cpu clock (that is one of the timer's clock indirect parent) now changes, along with the actual sched_clock rate. We can safely remove the sched_clock on those systems, since we have other reliable sched_clock in the system. Signed-off-by: Maxime Ripard Signed-off-by: Daniel Lezcano Tested-by: Hans de Goede --- drivers/clocksource/timer-sun5i.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c index 5dcbf90..58597fb 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -137,11 +136,6 @@ static struct irqaction sun5i_timer_irq = { .dev_id = &sun5i_clockevent, }; -static u64 sun5i_timer_sched_read(void) -{ - return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1)); -} - static void __init sun5i_timer_init(struct device_node *node) { struct reset_control *rstc; @@ -172,7 +166,6 @@ static void __init sun5i_timer_init(struct device_node *node) writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(1)); - sched_clock_register(sun5i_timer_sched_read, 32, rate); clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name, rate, 340, 32, clocksource_mmio_readl_down);