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[2001:1868:205::9]) by mx.google.com with ESMTPS id r9si7512441igh.88.2015.09.18.09.29.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Sep 2015 09:29:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyWF-0002eq-Np; Fri, 18 Sep 2015 16:28:15 +0000 Received: from merlin.infradead.org ([205.233.59.134]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyVi-00023v-33 for linux-arm-kernel@bombadil.infradead.org; Fri, 18 Sep 2015 16:27:42 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1ZcyVe-0001RY-Te for linux-arm-kernel@lists.infradead.org; Fri, 18 Sep 2015 16:27:39 +0000 Received: by padhk3 with SMTP id hk3so55050626pad.3 for ; Fri, 18 Sep 2015 09:27:14 -0700 (PDT) X-Received: by 10.66.254.201 with SMTP id ak9mr7886180pad.151.1442593634606; Fri, 18 Sep 2015 09:27:14 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.13 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:14 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Subject: [RFC PATCH 09/20] coresight: etb10: implementing buffer update API Date: Fri, 18 Sep 2015 10:26:23 -0600 Message-Id: <1442593594-10665-10-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_122739_128442_C896C862 X-CRM114-Status: GOOD ( 24.63 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.49 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: al.grant@arm.com, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Implementing buffer API to update the location of the ETB internal ring buffer once a trace session has ended. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 113 ++++++++++++++++++++++++++ include/linux/coresight.h | 3 + 2 files changed, 116 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 3239036f4609..043e504837d3 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -346,12 +346,125 @@ static void etb_unset_buffer(struct coresight_device *csdev, local_xchg(&buf->lost, 0)); } +static void etb_update_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle) +{ + int i, cur; + u8 *buf_ptr; + u32 read_ptr, write_ptr, start; + u32 status, read_data, words; + unsigned long flags, offset; + struct cs_buffers *buf = perf_get_aux(handle); + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + if (!buf) + return; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (!drvdata->enable) + goto out; + + etb_disable_hw(drvdata); + CS_UNLOCK(drvdata->base); + + read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); + write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); + + /* + * Entries should be aligned to the frame size. If they are not + * go back to the last alignement point to give decoding tools a + * chance to fix things. + */ + if (write_ptr % ETB_FRAME_SIZE_WORDS) { + dev_err(drvdata->dev, + "write_ptr: %lu not aligned to formatter frame size\n", + (unsigned long)write_ptr); + + write_ptr &= ~ETB_FRAME_SIZE_WORDS; + local_inc(&buf->lost); + } + + /* + * Get a hold of the status register and see if a wrap around + * has occurred. If so adjust things accordingly. Otherwise + * start at the beginning and go until the write pointer has + * been reached. + */ + status = readl_relaxed(drvdata->base + ETB_STATUS_REG); + if (status & ETB_STATUS_RAM_FULL) { + local_inc(&buf->lost); + words = drvdata->buffer_depth; + start = write_ptr; + } else { + words = write_ptr - read_ptr; + start = 0; + } + + /* + * Make sure we don't overwrite data that hasn't been consumed yet. + * It is entirely possible that the HW buffer has more data than the + * ring buffer can currently handle. If so adjust the start address + * to take only the last traces. + * + * Since metrics related to ETBs is in words, multiply by the + * amount of byte per word to have the right units. + */ + if (words * ETB_FRAME_SIZE_WORDS > handle->size) { + unsigned int capacity = drvdata->buffer_depth; + + /* make sure new sizes are still multiples the frame size */ + words = handle->size / ETB_FRAME_SIZE_WORDS; + /* advance the start pointer to get the latest trace data */ + start += capacity - words; + /* wrap around if we've reach the end of the HW buffer */ + start &= capacity - 1; + /* let the decoder know we've skipped ahead */ + local_inc(&buf->lost); + } + + /* finally tell HW where we want to start reading from */ + writel_relaxed(start, drvdata->base + ETB_RAM_READ_POINTER); + + cur = buf->cur; + offset = buf->offset; + for (i = 0; i < words; i++) { + buf_ptr = buf->addr[cur] + offset; + read_data = readl_relaxed(drvdata->base + + ETB_RAM_READ_DATA_REG); + *buf_ptr++ = read_data >> 0; + *buf_ptr++ = read_data >> 8; + *buf_ptr++ = read_data >> 16; + *buf_ptr++ = read_data >> 24; + + offset += 4; + if (offset >= PAGE_SIZE) { + offset = 0; + cur++; + /* wrap around at the end of the buffer */ + cur &= buf->nr_pages - 1; + } + } + + /* reset ETB buffer for next run */ + writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); + writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); + + /* update ring buffer information */ + local_add(words * ETB_FRAME_SIZE_WORDS, &buf->data_size); + + CS_LOCK(drvdata->base); + etb_enable_hw(drvdata); +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); +} + static const struct coresight_ops_sink etb_sink_ops = { .enable = etb_enable, .disable = etb_disable, .setup_aux = etb_setup_aux, .set_buffer = etb_set_buffer, .unset_buffer = etb_unset_buffer, + .update_buffer = etb_update_buffer, }; static const struct coresight_ops etb_cs_ops = { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 25bdce345ec3..48c3b9df0ae0 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -187,6 +187,7 @@ struct coresight_device { * @enable: enables the sink. * @disable: disables the sink. * @setup_aux: initialises perf's ring buffer for trace collection. + * @update_buffer: update buffer pointers after a trace session. * @set_buffer: initialises buffer mechanic before a trace session. * @unset_buffer: finalises buffer mechanic after a trace session. */ @@ -195,6 +196,8 @@ struct coresight_ops_sink { void (*disable)(struct coresight_device *csdev); void *(*setup_aux)(struct coresight_device *csdev, int cpu, void **pages, int nr_pages, bool overwrite); + void (*update_buffer)(struct coresight_device *csdev, + struct perf_output_handle *handle); int (*set_buffer)(struct coresight_device *csdev, struct perf_event *event, struct perf_output_handle *handle);