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BLUPR12MB0436; 5:2Nm7Djg/duL/0CzPr0MklQcGX9oEclDZidH5N0hunEr85t9qixaEsLRWqun0JQR227kt1YvB85Q+DWwUCQCcBlrEz/GBJjwF/annN4td3khC901/+oIMRdckMPhK3sD6iXHylaIpqZIPPxTCapbJJA==; 24:MgXmyoRkckX/h/5nKCsr5cCjv6z/+zr0OWugYQohjhPMFT/0OXC1aDtxUuOL5OlLbiz3aTcmrKt3/1Ue2/EYnweW7tsVBeUEMBal4q2rjzI=; 20:W4mefvjwydemyckcB9yWJ6OBAOuOLLtns3KxzsUMzSvkp2TD3P2KHKQJC+MRtp3n28sFuwCskab0ARBde6WojQk8OKC/gPyxqVy0JD4+R4Lsy5lmxoTLNnJhi2OU2Dijtw6sq3830ehZf4ypaA8VGUhHH8gvtIRWDhiaLALf2SjKERjf74eV/pvtjQmwnQDfQjdl+Mg82GrztepBM6O/zsrsQzggD4JzN4NexMqz3PUglKItrstG8WItadN8LReW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2016 14:13:42.0833 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR12MB0436 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch contains the follow minor fixup: * Fixed overflow handling since u64 delta would lose the MSB sign bit. * Remove unnecessary local64_set(). * Coding style and make use of GENMASK_ULL macro. Cc: Peter Zijlstra Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) -- 1.9.1 diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 629bc70..9da0d16 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -314,9 +314,8 @@ static void perf_iommu_start(struct perf_event *event, int flags) static void perf_iommu_read(struct perf_event *event) { - u64 count = 0ULL; - u64 prev_raw_count = 0ULL; - u64 delta = 0ULL; + u64 cnt, prev; + s64 delta; struct hw_perf_event *hwc = &event->hw; pr_debug("perf: amd_iommu:perf_iommu_read\n"); @@ -325,18 +324,20 @@ static void perf_iommu_read(struct perf_event *event) IOMMU_PC_COUNTER_REG, &count, false); /* IOMMU pc counter register is only 48 bits */ - count &= 0xFFFFFFFFFFFFULL; + cnt &= GENMASK_ULL(48, 0); - prev_raw_count = local64_read(&hwc->prev_count); - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - count) != prev_raw_count) - return; + prev = local64_read(&hwc->prev_count); - /* Handling 48-bit counter overflowing */ - delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT); + /* + * Since we do not enable counter overflow interrupts, + * we do not have to worry about prev_count changing on us. + */ + local64_set(&hwc->prev_count, cnt); + + /* Handle 48-bit counter overflow */ + delta = (cnt << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); delta >>= COUNTER_SHIFT; local64_add(delta, &event->count); - } static void perf_iommu_stop(struct perf_event *event, int flags)