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c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:To:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=+v5y78yO0d7Ij3270WDPuRiPAh+fjTBxr1W7JSIvqXc=; b=MoCXFxpFu3AyT1coUkgESKTcmVxA3MB1UHicVpmtesrT+kMnZK5gmxrC4K+ob3BhM3bRwqXpgAp3xt6mYcfEIFUFKQJkoVrf9aoL3nRkykkglvP6wQJjbVao8/XBxoAyq0Fbjl/CfRQ2nuGKOkG1aN9lnGCuZik4efsxrqDDK/o= Authentication-Results: redhat.com; dkim=none (message not signed) header.d=none; redhat.com; dmarc=none action=none header.from=amd.com; Received: from localhost.localdomain (124.121.8.20) by SN1PR12MB0446.namprd12.prod.outlook.com (10.162.105.14) with Microsoft SMTP Server (TLS) id 15.1.453.26; Fri, 8 Apr 2016 12:50:27 +0000 From: Suravee Suthikulpanit To: , , , , , CC: , , , , Suravee Suthikulpanit Subject: [PART2 RFC v1 9/9] svm: Update AMD IOMMU IRTE with vcpu scheduling information when enable AVIC Date: Fri, 8 Apr 2016 07:49:30 -0500 Message-ID: <1460119770-2896-10-git-send-email-Suravee.Suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460119770-2896-1-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1460119770-2896-1-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [124.121.8.20] X-ClientProxiedBy: HKNPR06CA0022.apcprd06.prod.outlook.com (10.141.16.12) To SN1PR12MB0446.namprd12.prod.outlook.com (10.162.105.14) X-MS-Office365-Filtering-Correlation-Id: 7283daad-9319-4b95-787e-08d35fac5e21 X-Microsoft-Exchange-Diagnostics: 1; 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SN1PR12MB0446; 5:TvkgIFn9/uQe70vfl+ZBx3E45WVdQ3tUd8DaKBLCOvhZH1PdEOiyDea+q3Y2jmfLgYGvQjZN8mOlJrb5Jll+kleRS34u/4n9k4glRGdNeHOlcH5i0R6ivLwQ9ysZwlp+3ypGFxL3NJPs3ShDFvOqsQ==; 24:rAkMy8g0UXig0f4bKLAHizvMDART2YtvfqVY4He3iarvvRDe3gJIOX85VdZxj1DxC0FhIdmwh3RpX0xar5L13wubyH2R8WPzzVFoRvyiQEk=; 20:mH5h/KxauuAAuZQFPXFFWFWfBFKv9DermSRdau9m4oC8y2mbxGo1pb7CFIvzFRJtLNvfUK+Z7RQMjFy806tU9r9417F5RdrbZBgWJ3TDZjizC792QsFgBCMzzjnV5HytJ7v06SkZbPO3iUajiUZF/4KhK1pJ3+t0IK7Z+74Bh4/Hw2y45tMSYusaWUsZL7C7rEeS3/51NToy3HJqBYD4aA4rTKO0glSWeBQMfMuQ4dpovpp7jdz2CnXRJsa0b8aZ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2016 12:50:27.3261 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB0446 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suravee Suthikulpanit In case AVIC is enabled, during vcpu_load/unload, SVM needs to update IOMMU IRTE with appropriate host physical APIC ID. Also, when vcpu_blocking/unblocking, SVM needs to update the is-running bit in the IOMMU IRTE. Both are achieved via calling amd_iommu_update_ga(). However, if GA mode is not enabled for the pass-through device, IOMMU driver will simply just return when calling amd_iommu_update_ga. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 50 +++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 7 deletions(-) -- 1.9.1 diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 38fd7a3..3b9a0b2 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1397,11 +1397,24 @@ free_avic: return err; } +static inline int +avic_update_iommu(struct kvm_vcpu *vcpu, int cpu, phys_addr_t pa, bool r) +{ + struct kvm_arch *vm_data = &vcpu->kvm->arch; + + if (!kvm_arch_has_assigned_device(vcpu->kvm)) + return 0; + + return amd_iommu_update_ga(vcpu->vcpu_id, cpu, vm_data->avic_tag, + (pa & AVIC_HPA_MASK), r); +} + /** * This function is called during VCPU halt/unhalt. */ static int avic_set_running(struct kvm_vcpu *vcpu, bool is_run) { + int ret = 0; u64 entry; int h_physical_id = __default_cpu_present_to_apicid(vcpu->cpu); struct vcpu_svm *svm = to_svm(vcpu); @@ -1420,17 +1433,27 @@ static int avic_set_running(struct kvm_vcpu *vcpu, bool is_run) WARN_ON((entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) == 0); entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - if (is_run) + if (is_run) { entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + WRITE_ONCE(*(svm->avic_physical_id_cache), entry); - return 0; + ret = avic_update_iommu(vcpu, h_physical_id, + page_to_phys(svm->avic_backing_page), 1); + } else { + ret = avic_update_iommu(vcpu, h_physical_id, + page_to_phys(svm->avic_backing_page), 0); + + WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + } + + return ret; } static int avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu, bool is_load) { - u64 entry; + int ret = 0; int h_physical_id = __default_cpu_present_to_apicid(cpu); + u64 entry; struct vcpu_svm *svm = to_svm(vcpu); if (!svm_vcpu_avic_enabled(svm)) @@ -1443,16 +1466,29 @@ static int avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu, bool is_load) entry = READ_ONCE(*(svm->avic_physical_id_cache)); WARN_ON(is_load && (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)); - entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; if (is_load) { entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); + + entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; if (!svm->avic_is_blocking) entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; + WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + + ret = avic_update_iommu(vcpu, h_physical_id, + page_to_phys(svm->avic_backing_page), + !svm->avic_is_blocking); + } else { + if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) { + ret = avic_update_iommu(vcpu, h_physical_id, + page_to_phys(svm->avic_backing_page), 0); + + entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; + WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + } } - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); - return 0; + return ret; } static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)