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[209.132.180.67]) by mx.google.com with ESMTP id u86si649971pfa.250.2016.04.12.16.59.43; Tue, 12 Apr 2016 16:59:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966831AbcDLX70 (ORCPT + 29 others); Tue, 12 Apr 2016 19:59:26 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:33042 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964905AbcDLX7W (ORCPT ); Tue, 12 Apr 2016 19:59:22 -0400 Received: by mail-pa0-f44.google.com with SMTP id zm5so22477329pac.0 for ; Tue, 12 Apr 2016 16:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cl7D2b+tgq9FOuGmHci4comxjtxD/olLRyqHR7He7WQ=; b=cvsx2jmt32csSIvmHJKZVfYUlGt+2I1u9Zv/ZIXHEatt39jCzsstooS3RRbk9HtLAk vVSyFgpkOZK/jA1kdrLb8WME0gDwWwpRdA/2tLY2b4bchcoTbkkHtkmMnF+vOmE8HB7V qQODIgB8HkE43MJTpEstp406zbDnqyvJOoB+o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cl7D2b+tgq9FOuGmHci4comxjtxD/olLRyqHR7He7WQ=; b=LnJfQzuvUxHKra5n3KF8cg3vZvjBiJy1KBOBFKfdl9WN7mwI0wDbpTsZdA6X54kSTa 5hEZ3fuWonjOeWlE4SwH3sPSIAGcEJz/OOzAGUlxvY7q88llVzngJIHSAgHM7/dPrxkK 20L6WgR1y+06MWTjzrB2J+E0TOvMCwzFHdU0++nGEJ6S3JfH7/Bt+nUpfakrRq/VRE6r XUlCyC/Zo8GrmcWYkAD1x6AJJVK453ctrHRMwGd6s9iNXByRVI1I1uZ605V62l+w6iSY HXHxuLzcR393OB6gOONK5oL1TLZY+qcyMIVgrbI8FMzvFE5XYns5ZAB1K2b7BDoyk5sG YJUA== X-Gm-Message-State: AOPr4FUDVU+ocdM1OcY7XExGO9SFjFd915RMe7dc7Py2MxTkfLMRE3xQm9qK/Hk1wmP7L+W9 X-Received: by 10.66.220.162 with SMTP id px2mr8569852pac.15.1460505562124; Tue, 12 Apr 2016 16:59:22 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.226]) by smtp.gmail.com with ESMTPSA id i1sm46165795pfj.17.2016.04.12.16.59.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Apr 2016 16:59:21 -0700 (PDT) From: Guodong Xu To: xuwei5@hisilicon.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, catalin.marinas@arm.com, will.deacon@arm.com, haojian.zhuang@linaro.org, linus.walleij@linaro.org, tony@atomide.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Guodong Xu Subject: [PATCH v4 12/16] arm64: dts: hi6220: add pinctrl for uarts and enable them Date: Wed, 13 Apr 2016 07:55:48 +0800 Message-Id: <1460505352-13157-13-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460505352-13157-1-git-send-email-guodong.xu@linaro.org> References: <1460505352-13157-1-git-send-email-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 12 ++++++++++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 3dbf51b..30c92bd 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -53,6 +53,18 @@ i2c1: i2c@f7101000 { status = "ok"; }; + + uart1: uart@f7111000 { + status = "ok"; + }; + + uart2: uart@f7112000 { + status = "ok"; + }; + + uart3: uart@f7113000 { + status = "ok"; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3a665ef..e8bb81f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -266,6 +266,8 @@ clocks = <&sys_ctrl HI6220_UART1_PCLK>, <&sys_ctrl HI6220_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; status = "disabled"; }; @@ -276,6 +278,8 @@ clocks = <&sys_ctrl HI6220_UART2_PCLK>, <&sys_ctrl HI6220_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; status = "disabled"; }; @@ -286,6 +290,9 @@ clocks = <&sys_ctrl HI6220_UART3_PCLK>, <&sys_ctrl HI6220_UART3_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; }; uart4: uart@f7114000 { @@ -295,6 +302,8 @@ clocks = <&sys_ctrl HI6220_UART4_PCLK>, <&sys_ctrl HI6220_UART4_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; status = "disabled"; };