From patchwork Tue Jun 28 10:31:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 70988 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp1508760qgy; Tue, 28 Jun 2016 03:32:12 -0700 (PDT) X-Received: by 10.66.189.225 with SMTP id gl1mr510527pac.158.1467109932341; Tue, 28 Jun 2016 03:32:12 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x186si33012000pfx.201.2016.06.28.03.32.12; Tue, 28 Jun 2016 03:32:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752381AbcF1KcB (ORCPT + 30 others); Tue, 28 Jun 2016 06:32:01 -0400 Received: from mail-pf0-f172.google.com ([209.85.192.172]:34914 "EHLO mail-pf0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752281AbcF1Kb7 (ORCPT ); Tue, 28 Jun 2016 06:31:59 -0400 Received: by mail-pf0-f172.google.com with SMTP id c2so5622464pfa.2 for ; Tue, 28 Jun 2016 03:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=svoVkYTlK/84c2mNqVgdqLq/mrJG8eZrLUry9JTIIhE=; b=ZsEw0tNp1HeWLYWNj7fmQ87BthcXsg0FIGUbcGG70VwPlaR3cR39PwqaK7m2xSgmRS 0jP4VWJsD7410I4W6A8mDRiAm0fQR41zTj4cF3TH+StYctKkxibuuVIYRrBxBWt8nXOG 2yHvG3ug9mlX+4F8K5aRLsGnJbleQ7IiK+QKw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=svoVkYTlK/84c2mNqVgdqLq/mrJG8eZrLUry9JTIIhE=; b=XYgb0M3dhbda2gDFX6FORau+nRAOkJN90FrFqgvCphRmM7d+sWuoUc7eIRoRaO1WvI EvJl9Yg0wL5CsH0tx99V/K6e6wRKlm4iJV65MtEH+vnHNC56E4QKWp4dhC/UfO1kVwWE hBGkK7RtS6TjLAuxGoQRvi7WdqH7B9sjSAxEdnESqVyWw7J0KYal7YHpvYE+Am/S+Sgy z++DaYZXDdXyWLYeufvHDdXHCIJPE3/Jm4lRHgQznA+8lNAMjPubVNMatHQbnsRs4LdR vN44z4Uj9ltbCfJM7mPDoyc66ZrBiaItOrJTkOyMYZIQiRUkxCi4mRu/Oz+fDatFDI+t KlHw== X-Gm-Message-State: ALyK8tJbQuXgHv1n9NOpnAQZcW2MqAUjFi8gfyjBnXTiwfUcJ0Vl220/n+YBgg+Tf+WXuwCO X-Received: by 10.98.208.197 with SMTP id p188mr506632pfg.152.1467109918226; Tue, 28 Jun 2016 03:31:58 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.9]) by smtp.gmail.com with ESMTPSA id d8sm5801433pfg.72.2016.06.28.03.31.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Jun 2016 03:31:57 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, jorge.ramirez-ortiz@linaro.org, xinliang.liu@linaro.org, guodong.xu@linaro.org, john.stultz@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] clk: hi6220: initialize UART1 clock to 150MHz Date: Tue, 28 Jun 2016 18:31:42 +0800 Message-Id: <1467109902-17625-2-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467109902-17625-1-git-send-email-guodong.xu@linaro.org> References: <1467109902-17625-1-git-send-email-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jorge Ramirez-Ortiz Early at boot, during the sys_clk initialization, make sure UART1 uses the higher frequency clock. This enables support for higher baud rates (up to 3Mbps) required to support faster bluetooth transfers. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi6220.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index a36ffcb..55bd9bb 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -70,10 +71,10 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, }, }; +static struct hisi_clock_data *clk_data_ao; + static void __init hi6220_clk_ao_init(struct device_node *np) { - struct hisi_clock_data *clk_data_ao; - clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS); if (!clk_data_ao) return; @@ -192,6 +193,13 @@ static void __init hi6220_clk_sys_init(struct device_node *np) hi6220_clk_register_divider(hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); + + if (!clk_data_ao) + return; + + /* enable high speed clock on UART1 mux */ + clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC], + clk_data_ao->clk_data.clks[HI6220_150M]); } CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);