From patchwork Wed Jun 29 08:45:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 71170 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp2026075qgy; Wed, 29 Jun 2016 01:46:16 -0700 (PDT) X-Received: by 10.66.25.133 with SMTP id c5mr9555518pag.103.1467189976008; Wed, 29 Jun 2016 01:46:16 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bs7si3416527pab.49.2016.06.29.01.46.15; Wed, 29 Jun 2016 01:46:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752015AbcF2IqM (ORCPT + 30 others); Wed, 29 Jun 2016 04:46:12 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:34182 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751907AbcF2IqG (ORCPT ); Wed, 29 Jun 2016 04:46:06 -0400 Received: by mail-pf0-f182.google.com with SMTP id h14so16035951pfe.1 for ; Wed, 29 Jun 2016 01:46:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=62NBWjH7+92KKM7UO2Gfx1Bgx+w4WTsYBoMlzaRRk9k=; b=bl62A+pDHCT7hq2zZHQTfsr/pSdYEQbjR6jyy6eDeHOpdOrPKj9S2lhh46ZxIaT1us 5hwIhUiXLvCZN/PB8TCfoAxmgWzO//5xAbAIJovB9/59/7I/uUUtYcVV9IclL+TJXyII JrQkzoIu+a/pyRZ4EhfFYSBx/pm6V/8nb/IDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=62NBWjH7+92KKM7UO2Gfx1Bgx+w4WTsYBoMlzaRRk9k=; b=ka3J79U7QlR4d9eCCmiozTpu6eJazbUdJMSNE70/KBXe7QfDmddBsxUChJI30ge9Us ZQp4HtoVxszByEKkhACqF22bR9OE3jEAZF+iHd5SENvx/qKY8dJTfjZmCypSaXNhYQHk zujMWBlgkJwFMN4N96Pu5VY3YtI40iL1hCQyxhda6bD5TAKtl1uRtApzJ6J6i+fBB76y 7cjSoeTSRNdxvksq160V80954iqjdhMNKo70CoA43+eRfGOGPjXWsxVO6U+4V2UA03CV PtvdRjKO3QzTeNo2dTVSbLsLd/rIxJqvv8/YdWdC0iahgmKLOdmrjUpYO6KgR1k64UMh IuYQ== X-Gm-Message-State: ALyK8tL1R/WiR/zHmDlmCy0/ftE7b6O8IXT03JT0Wwjk+XNn21rMDoUa2T1dhJk0pRM5WI5r X-Received: by 10.98.73.69 with SMTP id w66mr9660023pfa.104.1467189965949; Wed, 29 Jun 2016 01:46:05 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.159]) by smtp.gmail.com with ESMTPSA id z88sm3857749pfa.59.2016.06.29.01.46.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Jun 2016 01:46:05 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, jorge.ramirez-ortiz@linaro.org, xinliang.liu@linaro.org, guodong.xu@linaro.org, john.stultz@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/2] clk: hi6220: Change syspll and media_syspll clk to 1.19GHz Date: Wed, 29 Jun 2016 16:45:54 +0800 Message-Id: <1467189955-21694-1-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xinliang Liu In the bootloader of HiKey/96boards, syspll and media_syspll clk was initialized to 1.19GHz. So, here changes it in kernel accordingly. 1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI (74.25MHz required by standards). Closer pixel clock means better compatibility to HDMI monitors. Signed-off-by: Guodong Xu Signed-off-by: Xinliang Liu --- drivers/clk/hisilicon/clk-hi6220.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index f02cb41..a36ffcb 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -34,8 +34,8 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = { { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, }, { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,}, { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,}, - { HI6220_PLL_SYS, "syspll", NULL, 0, 1200000000,}, - { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1200000000,}, + { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,}, + { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,}, { HI6220_DDR_SRC, "ddr_sel_src", NULL, 0, 1200000000,}, { HI6220_PLL_MEDIA, "media_pll", NULL, 0, 1440000000,}, { HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,},