From patchwork Wed Jun 29 08:45:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 71171 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp2026189qgy; Wed, 29 Jun 2016 01:46:33 -0700 (PDT) X-Received: by 10.98.134.15 with SMTP id x15mr9480314pfd.21.1467189993031; Wed, 29 Jun 2016 01:46:33 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fd8si3366537pac.265.2016.06.29.01.46.32; Wed, 29 Jun 2016 01:46:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752100AbcF2IqT (ORCPT + 30 others); Wed, 29 Jun 2016 04:46:19 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:36175 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751945AbcF2IqL (ORCPT ); Wed, 29 Jun 2016 04:46:11 -0400 Received: by mail-pa0-f46.google.com with SMTP id wo6so15437878pac.3 for ; Wed, 29 Jun 2016 01:46:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UKTxLiTlkJj/N8zJfC/WyfaogpqJJ2bJcGOR33wJ0lY=; b=fxm2mnwlVrcKL/cn9/LfbzFJ7DriRRfvSwLJMFvnQNVYoqh3bE8z3aQPaWNfYzwm3Z bi/n8XPavZnXIfUweqsgj3tF1/NGWNkE1jRQbMng4uzDIYKYIA1btSr4efa87n7XDGE1 XnFgMUAlNDJhQ49dPMTXe9ibNplFzb3BeXndQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UKTxLiTlkJj/N8zJfC/WyfaogpqJJ2bJcGOR33wJ0lY=; b=FVVgt4ntnWvAIqf2uSkBMruYhqLo6GwT1jQIrRC8oo31Mx3bmdMX7snHgKt4LXCrxs oGHjyDnjKTQLghJ6BMJ7kEAeF5m0mtdmVaOhrxuEzyiALOLLir2XwkykrVLaAA6tZpDK s2/nvRzcczSs3c5uoJ2valz8UMLaIuTY9AqZKQetuC2p+3JQDNOOBMYRbUhnb17aU/Ym kFtpcWZSLvyXoxWoO8lceek81FHinStRWq2FaBx7raFzbEbeMW1lvamGkvTStoha2J5I U1UEWaQo+kDng8mZ51UXX+gp2b0RN7zhuyYM9+6uSdnjNhQJW1JPPut/gB9gN8cKrW+c Mq0w== X-Gm-Message-State: ALyK8tJEWgaCuczwd+uGwzaX5fT8IRbdsBqHwd0Mv+dvjZylzpnFnGaOLDHVT7Q2uHWrqtoS X-Received: by 10.66.25.8 with SMTP id y8mr9628804paf.106.1467189970842; Wed, 29 Jun 2016 01:46:10 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.159]) by smtp.gmail.com with ESMTPSA id z88sm3857749pfa.59.2016.06.29.01.46.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Jun 2016 01:46:10 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, jorge.ramirez-ortiz@linaro.org, xinliang.liu@linaro.org, guodong.xu@linaro.org, john.stultz@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/2] clk: hi6220: initialize UART1 clock to 150MHz Date: Wed, 29 Jun 2016 16:45:55 +0800 Message-Id: <1467189955-21694-2-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467189955-21694-1-git-send-email-guodong.xu@linaro.org> References: <1467189955-21694-1-git-send-email-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jorge Ramirez-Ortiz Early at boot, during the sys_clk initialization, make sure UART1 uses the higher frequency clock, 150MHz. This enables support for higher baud rates (up to 3Mbps) in UART1, which is required by faster bluetooth transfers. v2: use clk_set_rate() to propergate clock settings. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi6220.c | 4 ++++ 1 file changed, 4 insertions(+) -- 1.9.1 diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index a36ffcb..631c56f 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -192,6 +193,9 @@ static void __init hi6220_clk_sys_init(struct device_node *np) hi6220_clk_register_divider(hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); + + if (clk_set_rate(clk_data->clk_data.clks[HI6220_UART1_SRC], 150000000)) + pr_err("failed to set uart1 clock rate\n"); } CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);