From patchwork Tue May 16 10:25:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 99858 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1945189qge; Tue, 16 May 2017 03:26:42 -0700 (PDT) X-Received: by 10.84.198.36 with SMTP id o33mr14896636pld.145.1494930402587; Tue, 16 May 2017 03:26:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494930402; cv=none; d=google.com; s=arc-20160816; b=XNGnViwyD80v0KYUaJw+bv9PLPGozJlmH5pwfFoR8py7V43vdRBIlIVD+vUR4SGy2Q 9JkzMgbyCHw1UPVtSuDpF6vc9X/v0K0CTomqI6Gj3RvH5zvs1eFIe+4thaqcAcJLatv8 Wl7cqH+9qwh69R97NGcBERNhcNcLxFYTl0QXLZLAFxE6/ZzBpli9IUjXIReYcnzqpvaX vVA62OGD5gb72iCOblKetfnK5WfU0jzGGsLOZmWH80oYzBofIQ0PZZ08tEvL7jJOeDdN 8mOHJGMPvxKi0Q+WZZEfBA9GQ0JzJian2YjwAB/5ikGNCWRd8HstTgyyFajyeiJxviHA Lz8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=zoNmORTYZpMY7em6OWeg5wMZOvsM1mLZJZbKtv35EJw=; b=N5wFc9H3HY5/q38/eCqPZmNqyDJGuLYe6pa5onMO7sO1DDKGhuyebP6qV0QlXMf0mL HGrPi2APVrUz+5IorXgvlUDGHBEFrAv7pASly6KaL3Y95BbOXwggzk0wC7+WzblZkT4W 72VqfBbIRBb6GFDIiW0kXbDkx4md5Bql3eAtM3E5MG0ct85DA8+9/3hAZYtvr8paAksS tdd+STzLG1phdtxMmasEX4F7Sj0eMV4/38w3O2XMGLunucpQtXBuZ1raxBhzb3g7XZzz Mf95doGVanrkoK9XNwGuAgtaoFdYdzTVOQnik1HbmDoKkj4jUOmSs7QreaDxnT29BzY4 dL1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si13398788pgp.311.2017.05.16.03.26.42; Tue, 16 May 2017 03:26:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752610AbdEPK0g (ORCPT + 25 others); Tue, 16 May 2017 06:26:36 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6305 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751943AbdEPK0M (ORCPT ); Tue, 16 May 2017 06:26:12 -0400 Received: from 172.30.72.56 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOP94150; Tue, 16 May 2017 18:26:08 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.162) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Tue, 16 May 2017 18:25:59 +0800 From: Gabriele Paoloni To: , CC: , , , , , Subject: [PATCH 2/2] PCI/portdrv: allocate MSI/MSIx vector for DPC RP service Date: Tue, 16 May 2017 11:25:42 +0100 Message-ID: <1494930342-7132-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1494930342-7132-1-git-send-email-gabriele.paoloni@huawei.com> References: <1494930342-7132-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.162] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.591AD3C1.0127, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ad04440f7dff792cf9c6f0d5cffca65e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni Currently the MSI/MSIx vectors for the root port services are allocated calling pcie_init_service_irqs(). At the moment these vectors are only allocated for AER, PME, HP. This patch allocate an MSI/MSIx vector also for DPC. Signed-off-by: Liudongdong Signed-off-by: Gabriele Paoloni --- drivers/pci/pcie/portdrv_core.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.7.4 Reviewed-by: Christoph Hellwig diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e2c7bfd..477bf14 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -131,6 +131,35 @@ int pcie_port_enable_msix_or_msi(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * The code below follows Section 6.2.10.1 of the PCI Express + * Base Specification 4.0 stating that bits 4-0 of DPC + * Capability Register contain a value indicating which of the + * MSI/MSI-X vectors assigned to the port is going to be used + * for DPC, where "For MSI-X, the value in this register + * indicates which MSI-X Table entry is used to generate the + * interrupt message." and "For MSI, the value in this field + * indicates the offset between the base Message Data and the + * interrupt message that is generated." + * + * pci_irq_vector() below is able to handle entry differently + * depending on MSI vs MSI-x case + * + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the