From patchwork Thu May 18 09:01:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100059 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp620056qge; Thu, 18 May 2017 02:02:39 -0700 (PDT) X-Received: by 10.99.172.9 with SMTP id v9mr3333302pge.60.1495098159506; Thu, 18 May 2017 02:02:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495098159; cv=none; d=google.com; s=arc-20160816; b=E9rjeVNaV+1LHgSz8+K0y8juBScQUSkcvxGawteZ8QS3Fr9PYKPobbSxOQ1tasVb0M UANQ6g8qQ9ABFo89zjKhSFJj3SSVMlXGZtdok7v66k49XIw9gregqiDp0macf0qFHTZA OaTliUQU8RIPyHCxwTHIt0y7qJw8uR7JRuT9hYpGFV4BNi86zgMmyV+/7CmAg3KpyEUC hhNoQoCm73/e3b6WHwZNkkMdOxk7GhEe8FdBcDMlgGnt8IDSO10rAW3qc6TZ62OFbjUN ijP557UgyAkwmZzLDkRWXOM5m5YTnMnRzRRhHyFEHMZAJb2/H1zSCJyeMHuBKZzRHt6+ nkMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=9gk5Ygq51yhyaNVyB5gbOMKXyWhiWe/cdg439eALGfU=; b=pasUA6sP02dPb8qJJE4pXJDXWotiYuuLHOaUaE/mO17hbfE8HkDf6bRVe9h6yoMSG9 ivG3I/sTButAhqgQw7uSEVbWJCeYz6jQxXx8gjxlSLMQWKL1WJmN0Xm/YP9mmxbQgePU C332BhmSjqSBGLHUfnN2RgCqvMm7xlhyAah5xl0LvnJU6tZ14h2LhlLSnDrA6EPzZqwW V3M7B8hsoXQJwB6fkA8sX9slh0ModFlVfWd6oxn+jvk/L0S6rtt4s3FPUhK/wsiLgOlW b6qAWL/etaAedb1jJ+uS1oewYEBT4o+IZ1YbiQMkBmRYuqZBEV9gm7pwBRzdDyG9quhA 6ECw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y133si4684726pfg.257.2017.05.18.02.02.39; Thu, 18 May 2017 02:02:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754567AbdERJCR (ORCPT + 25 others); Thu, 18 May 2017 05:02:17 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6351 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751486AbdERJCM (ORCPT ); Thu, 18 May 2017 05:02:12 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ANU67978; Thu, 18 May 2017 17:02:05 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.162) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Thu, 18 May 2017 17:01:58 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v2 2/2] PCI/portdrv: allocate MSI/MSIx vector for DPC RP service Date: Thu, 18 May 2017 10:01:38 +0100 Message-ID: <1495098098-1984-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495098098-1984-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495098098-1984-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.162] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.591D630E.0014, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 48800a22a1dbad301fcbd233ca3c176b Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni Currently the MSI/MSIx vectors for the root port services are allocated calling pcie_init_service_irqs(). At the moment these vectors are only allocated for AER, PME, HP. This patch allocate an MSI/MSIx vector also for DPC. Signed-off-by: Liudongdong Signed-off-by: Gabriele Paoloni --- drivers/pci/pcie/portdrv_core.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.7.4 Reviewed-by: Christoph Hellwig diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 254bc73..4a8a1df 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -126,6 +126,31 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * The code below follows Section 6.2.10.1 of the PCI Express + * Base Specification 4.0 stating that bits 4-0 of DPC + * Capability Register contain a value indicating which of the + * MSI/MSI-X vectors assigned to the port is going to be used + * for DPC, where "For MSI-X, the value in this register + * indicates which MSI-X Table entry is used to generate the + * interrupt message." and "For MSI, the value in this field + * indicates the offset between the base Message Data and the + * interrupt message that is generated." + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the