From patchwork Mon May 22 14:06:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100303 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp1413565obb; Mon, 22 May 2017 07:07:51 -0700 (PDT) X-Received: by 10.99.167.15 with SMTP id d15mr8310171pgf.228.1495462071537; Mon, 22 May 2017 07:07:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495462071; cv=none; d=google.com; s=arc-20160816; b=D11yLNSXRlCXT7bnbES5kfMtRp12bbmZG9i8EZaNMdIcw31NZ+7zyF21B4T2nfCabz JtdwCCxNFcXzs7mPXbjkES0gCDTrfjgQNQ7410U0wJGqwVxWPLkNL2vZrCuqVdqP7nMT OlfFV01KhzYSJx6lOmnd8oQSynkppO4NZ5AbFEEl9FfuOG/jkmuPzj/bVZfngU4l/ALc OhnzNQtCSuT8GY2vhdtUPR7Y8gAq5//rPJJ3zHEq576ePMQLxpR+RFsVE0rpoJi8+a2e ki23MF+UED3TBDzB1g0VzgB5ticxwtH3TVtSIJ12PqXAw7bs5Ju7yiTBSKEuLGcMYvxU domw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=mi95mBWPRI/+OkDza++N2/p/+SyOK3HYb6lOhuvbW64=; b=N7VvTe8yqjLxAdLUs1n8uTPhynyBmjaqiNUTK0c4qDl62FFjUnje3Zmfku0y1VvxJy v/tyzLmruOTbAeMeXdaZMsTSQPJSFdN3yBt7C6lEw4f8dQxkf38238J9OyKmG1qet0wN EiM2KdHMdYmQ45C4S89wkVkz1S4AZaCqFCK1P9FLjfh41hniMRW9gpe2Zj6HPAKhV7ms rWZVzKazyWSd1Dbp2A9deWQe5JedbeKO2mnYpgAObvVgnij8rrnJCvCBc2jjIqcQqNPy 6b2VtrXqgQJQ5mYjUJLp0NezGRkcLarrmxyw7Y5juCIh/KGhM1WGTyW1pZtiebTXkLfc XJGw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f16si4126467plk.239.2017.05.22.07.07.51; Mon, 22 May 2017 07:07:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934174AbdEVOHp (ORCPT + 25 others); Mon, 22 May 2017 10:07:45 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6436 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933922AbdEVOHk (ORCPT ); Mon, 22 May 2017 10:07:40 -0400 Received: from 172.30.72.55 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOC40780; Mon, 22 May 2017 22:07:28 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.156) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Mon, 22 May 2017 22:07:18 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v4 2/2] PCI/portdrv: allocate MSI/MSIx vector for DPC RP service Date: Mon, 22 May 2017 15:06:58 +0100 Message-ID: <1495462018-7756-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495462018-7756-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495462018-7756-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.156] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.5922F0A0.0402, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 93d11a7f404513e5178b6d706af0d2e9 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni Currently the MSI/MSIx vectors for the root port services are allocated calling pcie_init_service_irqs(). At the moment these vectors are only allocated for AER, PME, HP. This patch allocate an MSI/MSIx vector also for DPC. Signed-off-by: Liudongdong Signed-off-by: Gabriele Paoloni Reviewed-by: Christoph Hellwig --- drivers/pci/pcie/portdrv_core.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.7.4 diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e5d5ffe..e422006 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -121,6 +121,31 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * The code below follows Section 6.2.10.1 of the PCI Express + * Base Specification 4.0 stating that bits 4-0 of DPC + * Capability Register contain a value indicating which of the + * MSI/MSI-X vectors assigned to the port is going to be used + * for DPC, where "For MSI-X, the value in this register + * indicates which MSI-X Table entry is used to generate the + * interrupt message." and "For MSI, the value in this field + * indicates the offset between the base Message Data and the + * interrupt message that is generated." + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the