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[209.132.180.67]) by mx.google.com with ESMTP id y62si2885312pff.159.2017.06.06.05.44.39; Tue, 06 Jun 2017 05:44:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751552AbdFFMob (ORCPT + 25 others); Tue, 6 Jun 2017 08:44:31 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:36953 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751431AbdFFMo3 (ORCPT ); Tue, 6 Jun 2017 08:44:29 -0400 Received: by mail-wm0-f43.google.com with SMTP id d73so48026392wma.0 for ; Tue, 06 Jun 2017 05:44:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lFGaAGzZYzKbX5d1R1FHW0G3UYMy2E11PyIUW1V1gAQ=; b=K0LQ1MgP3p1ncpvLJ79bZ0MuV9IEXJac6uw7HL+eU4WoRjxruekM4nvRY6j1ONHxJC O5D4A12tpwTIwiyHSmCqoJ9Omi4oNKNvDInAe0TkiH69cU04eW9kgQG8H/mrYyhSf3N6 5lIyBkef38ifB7SuU/V0YyUSQvRScX/TYqdic= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lFGaAGzZYzKbX5d1R1FHW0G3UYMy2E11PyIUW1V1gAQ=; b=Ea9QK97WWCShjNVbFBXm/5o9zIYDreViH7EhENjhdmeuBhBmqWKJPynShiJbkIaqD6 ZdbxldPWXBqVWnDRtdqinwkDaR3ABY711IwMwGtcO7/ov+uJC4knkcwtUZRMkH5P3xGq +C8XKqYiy7NH2Cgkkqtr9cfmNya/ceoOAu5YPLYSkuZTYIt3SQBG3IGdEfcDl14r7m0v mF5ouBqS1qYCtYJtn75LxyZB/eJtW82mx4LEyp9rHlVIqgZ84ip4FQgAfWsIC3W8a5C6 skO6EpsIWV2SrNbfLhsBXzYLx28pXPbmaxLtV3oAjI2mJQA+ZdOG0riubv8ObpBXJgFk g5VA== X-Gm-Message-State: AODbwcBbA3KO2QFI2BD8i9dTsDCEFxfIG2sw4Bv1oi1t2kmMLDBtrq/8 ssiyB/IRKlR9KQFm X-Received: by 10.28.28.146 with SMTP id c140mr12135101wmc.122.1496753068109; Tue, 06 Jun 2017 05:44:28 -0700 (PDT) Received: from localhost.localdomain ([2001:41d0:fe90:b800:3f16:bcf7:601c:a13b]) by smtp.gmail.com with ESMTPSA id w17sm6277827wra.34.2017.06.06.05.44.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Jun 2017 05:44:27 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Santosh Shilimkar Subject: [PATCH 2/2] clocksource/drivers/keystone: Use the timer-of common routine Date: Tue, 6 Jun 2017 14:44:12 +0200 Message-Id: <1496753054-7489-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496753054-7489-1-git-send-email-daniel.lezcano@linaro.org> References: <1496753054-7489-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The previous patch provided a common init routine for the OF drivers. The keystone driver is given as example on the improvement and usage of the common initialization routine. Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-keystone.c | 117 +++++++++++++---------------------- 2 files changed, 44 insertions(+), 74 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 4ba230d..f1ed520 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -216,6 +216,7 @@ config KEYSTONE_TIMER depends on GENERIC_CLOCKEVENTS depends on ARM || ARM64 select CLKSRC_MMIO + select TIMER_OF help Enables support for the Keystone timer. diff --git a/drivers/clocksource/timer-keystone.c b/drivers/clocksource/timer-keystone.c index 0eee032..84b2523 100644 --- a/drivers/clocksource/timer-keystone.c +++ b/drivers/clocksource/timer-keystone.c @@ -18,6 +18,8 @@ #include #include +#include "timer-of.h" + #define TIMER_NAME "timer-keystone" /* Timer register offsets */ @@ -37,26 +39,16 @@ #define TGCR_TIM_UNRESET_MASK 0x03 #define INTCTLSTAT_ENINT_MASK 0x01 -/** - * struct keystone_timer: holds timer's data - * @base: timer memory base address - * @hz_period: cycles per HZ period - * @event_dev: event device based on timer - */ -static struct keystone_timer { - void __iomem *base; - unsigned long hz_period; - struct clock_event_device event_dev; -} timer; +static struct timer_of to; static inline u32 keystone_timer_readl(unsigned long rg) { - return readl_relaxed(timer.base + rg); + return readl_relaxed(timer_of_base(&to) + rg); } static inline void keystone_timer_writel(u32 val, unsigned long rg) { - writel_relaxed(val, timer.base + rg); + writel_relaxed(val, timer_of_base(&to) + rg); } /** @@ -123,6 +115,7 @@ static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = dev_id; evt->event_handler(evt); + return IRQ_HANDLED; } @@ -140,43 +133,42 @@ static int keystone_shutdown(struct clock_event_device *evt) static int keystone_set_periodic(struct clock_event_device *evt) { - keystone_timer_config(timer.hz_period, TCR_ENAMODE_PERIODIC_MASK); + struct timer_of *to = to_timer_of(evt); + + keystone_timer_config(timer_of_period(to), TCR_ENAMODE_PERIODIC_MASK); + return 0; } +static struct timer_of to = { + .flags = TIMER_OF_IRQ | + TIMER_OF_CLOCK | + TIMER_OF_BASE, + + .clkevt = { + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = keystone_set_next_event, + .set_state_shutdown = keystone_shutdown, + .set_state_periodic = keystone_set_periodic, + .set_state_oneshot = keystone_shutdown, + .cpumask = cpu_all_mask, + .owner = THIS_MODULE, + .name = TIMER_NAME, + }, + + .of_irq = { + .handler = keystone_timer_interrupt, + }, +}; + static int __init keystone_timer_init(struct device_node *np) { - struct clock_event_device *event_dev = &timer.event_dev; - unsigned long rate; - struct clk *clk; - int irq, error; - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - pr_err("%s: failed to map interrupts\n", __func__); - return -EINVAL; - } - - timer.base = of_iomap(np, 0); - if (!timer.base) { - pr_err("%s: failed to map registers\n", __func__); - return -ENXIO; - } - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - pr_err("%s: failed to get clock\n", __func__); - iounmap(timer.base); - return PTR_ERR(clk); - } - - error = clk_prepare_enable(clk); - if (error) { - pr_err("%s: failed to enable clock\n", __func__); - goto err; - } - - rate = clk_get_rate(clk); + int ret; + + ret = timer_of_init(np, &to); + if (ret) + return ret; /* disable, use internal clock source */ keystone_timer_writel(0, TCR); @@ -193,38 +185,15 @@ static int __init keystone_timer_init(struct device_node *np) keystone_timer_writel(0, TIM12); keystone_timer_writel(0, TIM34); - timer.hz_period = DIV_ROUND_UP(rate, HZ); - /* enable timer interrupts */ keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT); - error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER, - TIMER_NAME, event_dev); - if (error) { - pr_err("%s: failed to setup irq\n", __func__); - goto err; - } - - /* setup clockevent */ - event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - event_dev->set_next_event = keystone_set_next_event; - event_dev->set_state_shutdown = keystone_shutdown; - event_dev->set_state_periodic = keystone_set_periodic; - event_dev->set_state_oneshot = keystone_shutdown; - event_dev->cpumask = cpu_all_mask; - event_dev->owner = THIS_MODULE; - event_dev->name = TIMER_NAME; - event_dev->irq = irq; - - clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX); - - pr_info("keystone timer clock @%lu Hz\n", rate); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + 1, ULONG_MAX); + + pr_info("keystone timer clock @%lu Hz\n", timer_of_rate(&to)); + return 0; -err: - clk_put(clk); - iounmap(timer.base); - return error; } -TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer", - keystone_timer_init); +TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer", keystone_timer_init);