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[209.132.180.67]) by mx.google.com with ESMTP id l186si3262129pge.602.2017.07.25.23.34.46; Tue, 25 Jul 2017 23:34:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751467AbdGZGeo (ORCPT + 26 others); Wed, 26 Jul 2017 02:34:44 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:10272 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750880AbdGZGej (ORCPT ); Wed, 26 Jul 2017 02:34:39 -0400 Received: from 172.30.72.56 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATB18028; Wed, 26 Jul 2017 14:30:07 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Wed, 26 Jul 2017 14:29:57 +0800 From: Jiancheng Xue To: , , , CC: , , , , , Jiancheng Xue Subject: [PATCH v2 1/4] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy Date: Wed, 26 Jul 2017 14:06:00 +0800 Message-ID: <1501049163-18892-2-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501049163-18892-1-git-send-email-xuejiancheng@hisilicon.com> References: <1501049163-18892-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.597836EF.011F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 34fe8d8a317cb9bad0da532d41a94db0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for hisi-inno-usb2 phy. Signed-off-by: Jiancheng Xue --- .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt new file mode 100644 index 0000000..417eeaa --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt @@ -0,0 +1,31 @@ +HiSilicon INNO USB2 PHY +----------------------- +Required properties: +- compatible: Should be one of the following strings: + "hisilicon,inno-usb2-phy", + "hisilicon,hi3798cv200-usb2-phy", +- #phy-cells: Shall be 0. +- hisilicon,peripheral-syscon: Phandle of syscon used to control phy. +- hisilicon,phycon-reg: Offset of the phy control register in the syscon. +- hisilicon,port-num: Number of utmi ports. Range [1,2]. +- clocks: Phandle and clock specifier pair for reference clock utmi_refclk. +- resets: List of phandle and reset specifier pairs for each reset signal +in reset-names. +- reset-names: Shall be "power_on", "utmi0", "utmi1". Thereinto, utmi[n] is +required only if port[n] exists. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Example: +usb2_phy: phy { + compatible = "hisilicon,inno-usb2-phy"; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peri_ctrl>; + hisilicon,phycon-reg = <0x120>; + hisilicon,port-num = <2>; + clocks = <&crg USB2_PHY_UTMI_REF_CLK>; + resets = <&crg 0xbc 2>, + <&crg 0xbc 8>, + <&crg 0xbc 9>, + reset-names = "power_on", "utmi0", "utmi1"; + };