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[209.132.180.67]) by mx.google.com with ESMTP id m23si7875184plk.953.2017.07.25.23.35.36; Tue, 25 Jul 2017 23:35:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751548AbdGZGfT (ORCPT + 26 others); Wed, 26 Jul 2017 02:35:19 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:10274 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750892AbdGZGej (ORCPT ); Wed, 26 Jul 2017 02:34:39 -0400 Received: from 172.30.72.56 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ATB18021; Wed, 26 Jul 2017 14:30:06 +0800 (CST) Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Wed, 26 Jul 2017 14:29:58 +0800 From: Jiancheng Xue To: , , , CC: , , , , , Jiancheng Xue Subject: [PATCH v2 3/4] arm64: dts: hisilicon: add usb2 controller and phy nodes for poplar board. Date: Wed, 26 Jul 2017 14:06:02 +0800 Message-ID: <1501049163-18892-4-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501049163-18892-1-git-send-email-xuejiancheng@hisilicon.com> References: <1501049163-18892-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.597836EE.0146, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 077156e7c239014b11252d1527199327 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add usb2 controller and phy nodes for poplar board. Signed-off-by: Jiancheng Xue Reviewed-by: Daniel Thompson --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 13 +++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 60 ++++++++++++++++++++++ 2 files changed, 73 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index b914287..4656ba9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -63,6 +63,10 @@ }; }; +&ehci { + status = "okay"; +}; + &gmac1 { status = "okay"; #address-cells = <1>; @@ -146,6 +150,10 @@ status = "okay"; }; +&ohci { + status = "okay"; +}; + &spi0 { status = "okay"; label = "LS-SPI0"; @@ -160,3 +168,8 @@ label = "LS-UART0"; }; /* No optional LS-UART1 on Low Speed Expansion Connector. */ + +&usb2_phy1 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 75865f8a..250b68b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -106,6 +106,11 @@ #reset-cells = <2>; }; + peri_ctrl: system-controller@8a20000 { + compatible = "syscon"; + reg = <0x8a20000 0x1000>; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; @@ -407,5 +412,60 @@ clocks = <&sysctrl HISTB_IR_CLK>; status = "disabled"; }; + + ehci: ehci@0x9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_PHY_CLK>, + <&crg HISTB_USB2_UTMI_CLK>; + clock-names = "ehci_system", "phy", "utmi"; + resets = <&crg 0xb8 12>, + <&crg 0xb8 16>, + <&crg 0xb8 13>; + reset-names = "bus", "phy", "utmi"; + status = "disabled"; + }; + + ohci: ohci@0x9880000 { + compatible = "generic-ohci"; + reg = <0x9880000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_12M_CLK>, + <&crg HISTB_USB2_48M_CLK>; + clock-names = "ahb_biu", "clk12", "clk48"; + resets = <&crg 0xb8 12>; + reset-names = "bus"; + status = "disabled"; + }; + + usb2_phy1: usb-phy@1 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peri_ctrl>; + hisilicon,phycon-reg = <0x120>; + hisilicon,port-num = <2>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>, + <&crg 0xbc 8>, + <&crg 0xbc 9>; + reset-names = "power_on", "utmi0", "utmi1"; + status = "disabled"; + }; + + usb2_phy2: usb-phy@2 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peri_ctrl>; + hisilicon,phycon-reg = <0x124>; + hisilicon,port-num = <1>; + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; + resets = <&crg 0xbc 6>, + <&crg 0xbc 10>; + reset-names = "power_on", "utmi0"; + status = "disabled"; + }; }; };