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[209.132.180.67]) by mx.google.com with ESMTP id i5-v6si23943618pgk.200.2018.09.20.12.19.16; Thu, 20 Sep 2018 12:19:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y7QG43wP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389039AbeIUBEM (ORCPT + 32 others); Thu, 20 Sep 2018 21:04:12 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:36732 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388558AbeIUBEL (ORCPT ); Thu, 20 Sep 2018 21:04:11 -0400 Received: by mail-pl1-f196.google.com with SMTP id p5-v6so4798819plk.3 for ; Thu, 20 Sep 2018 12:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jasPfZK2wsoNdBWcuDJHTJ/t7P13W2dMZ0nkyY04hwI=; b=Y7QG43wPm9TKE2tYCf0S6IUT4pUBEArOvbatjgDJCpuO05UTKAuke4NOpTovBSa/BX 3ntebuh3HLc1+DTTBVKYqSFq/tF1zUzslLACaS/48jgNnRfX0BanRmCuoIepFoHrswd+ qrdC05hgviCWwKtJU4Mc24cPiJtzaoHmhBHb4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jasPfZK2wsoNdBWcuDJHTJ/t7P13W2dMZ0nkyY04hwI=; b=a/tSdnBV8h8lgEkxEZ4QghFv2ita8rrLHZ5b+jbquymnOqHhryos+Dt4iGaZc6bEuT Q+S6eCMRui6T4ONf4oBPhLaGQzzJaIVcTXRJ9MmbTnifVfi3fx6oIfqQW/8s2xn0gMsL kq6nF1bJAnV9w0StqEPHMhDw5Gh1tVDWyYs07qrAuN9S49hnCRc6ZozIBkCaZEDO03vx b245X69Sh/L5h7GHNkmOCmZI8LatemUu3BpCYQzNA4gC5bIzVNoLWrxM9hqdY2okqvcL NkpfC13alXp7dsJ2Q7cCkEEy25A9GA0ey1I6fBdQbDXjU5GXVc79fQenGXz1PZ5UyeBu zgFg== X-Gm-Message-State: APzg51D2qW9jG+srVy+pugfkHPEiNMIDVSaC+XhL7kzYqM+S+aqIAl5D 8FJiT3uibk64Nq/lsYLkjuw+t0WUfS0= X-Received: by 2002:a17:902:24e1:: with SMTP id l30-v6mr40914387plg.315.1537471152152; Thu, 20 Sep 2018 12:19:12 -0700 (PDT) Received: from localhost.localdomain ([209.121.128.187]) by smtp.gmail.com with ESMTPSA id k13-v6sm4424443pgf.37.2018.09.20.12.19.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Sep 2018 12:19:11 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 33/44] coresight: etm3: Add support for handling errors Date: Thu, 20 Sep 2018 13:18:08 -0600 Message-Id: <1537471099-19781-34-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537471099-19781-1-git-send-email-mathieu.poirier@linaro.org> References: <1537471099-19781-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose Add support for reporting errors back from the SMP cross function call for enabling ETM. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 42 ++++++++++++++++++--------- 1 file changed, 28 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 9ce8fba20b0f..206c2381a11a 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -355,11 +355,10 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, return 0; } -static void etm_enable_hw(void *info) +static int etm_enable_hw(struct etm_drvdata *drvdata) { int i; u32 etmcr; - struct etm_drvdata *drvdata = info; struct etm_config *config = &drvdata->config; CS_UNLOCK(drvdata->base); @@ -421,6 +420,21 @@ static void etm_enable_hw(void *info) CS_LOCK(drvdata->base); dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); + return 0; +} + +struct etm_enable_arg { + struct etm_drvdata *drvdata; + int rc; +}; + +static void etm_enable_hw_smp_call(void *info) +{ + struct etm_enable_arg *arg = info; + + if (WARN_ON(!arg)) + return; + arg->rc = etm_enable_hw(arg->drvdata); } static int etm_cpu_id(struct coresight_device *csdev) @@ -475,14 +489,13 @@ static int etm_enable_perf(struct coresight_device *csdev, /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); /* And enable it */ - etm_enable_hw(drvdata); - - return 0; + return etm_enable_hw(drvdata); } static int etm_enable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct etm_enable_arg arg = { 0 }; int ret; spin_lock(&drvdata->spinlock); @@ -492,20 +505,21 @@ static int etm_enable_sysfs(struct coresight_device *csdev) * hw configuration will take place on the local CPU during bring up. */ if (cpu_online(drvdata->cpu)) { + arg.drvdata = drvdata; ret = smp_call_function_single(drvdata->cpu, - etm_enable_hw, drvdata, 1); - if (ret) - goto err; + etm_enable_hw_smp_call, &arg, 1); + if (!ret) + ret = arg.rc; + if (!ret) + drvdata->sticky_enable = true; + } else { + ret = -ENODEV; } - drvdata->sticky_enable = true; spin_unlock(&drvdata->spinlock); - dev_dbg(drvdata->dev, "ETM tracing enabled\n"); - return 0; - -err: - spin_unlock(&drvdata->spinlock); + if (!ret) + dev_dbg(drvdata->dev, "ETM tracing enabled\n"); return ret; }