@@ -87,6 +87,7 @@
#define VSIZE_OFST 20
#define LDI_INT_EN 0x741C
#define FRAME_END_INT_EN_OFST 1
+#define UNDERFLOW_INT_EN_OFST 2
#define LDI_CTRL 0x7420
#define BPP_OFST 3
#define DATA_GATE_EN BIT(2)
@@ -97,6 +98,11 @@
#define LDI_HDMI_DSI_GT 0x7434
/*
+ *BIT_LDI_UNFLOW
+ */
+#define BIT_LDI_UNFLOW BIT(2)
+
+/*
* ADE media bus service regs
*/
#define ADE0_QOSGENERATOR_MODE 0x010C
@@ -58,6 +58,7 @@ struct ade_hw_ctx {
struct ade_crtc {
struct drm_crtc base;
struct ade_hw_ctx *ctx;
+ struct work_struct drm_device_wq;
bool enable;
u32 out_format;
};
@@ -176,6 +177,7 @@ static void ade_init(struct ade_hw_ctx *ctx)
*/
ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
+ ade_update_bits(base + LDI_INT_EN, UNDERFLOW_INT_EN_OFST, MASK(1), 1);
}
static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
@@ -345,6 +347,17 @@ static void ade_crtc_disable_vblank(struct drm_crtc *crtc)
MASK(1), 0);
}
+static void drm_underflow_wq(struct work_struct *work)
+{
+ struct ade_crtc *acrtc = container_of(work, struct ade_crtc,
+ drm_device_wq);
+ struct drm_device *drm_dev = (&acrtc->base)->dev;
+ struct drm_atomic_state *state;
+
+ state = drm_atomic_helper_suspend(drm_dev);
+ drm_atomic_helper_resume(drm_dev, state);
+}
+
static irqreturn_t ade_irq_handler(int irq, void *data)
{
struct ade_crtc *acrtc = data;
@@ -362,6 +375,12 @@ static irqreturn_t ade_irq_handler(int irq, void *data)
MASK(1), 1);
drm_crtc_handle_vblank(crtc);
}
+ if (status & BIT_LDI_UNFLOW) {
+ ade_update_bits(base + LDI_INT_CLR, UNDERFLOW_INT_EN_OFST,
+ MASK(1), 1);
+ DRM_ERROR("LDI underflow!");
+ schedule_work(&acrtc->drm_device_wq);
+ }
return IRQ_HANDLED;
}
@@ -1038,6 +1057,9 @@ static int ade_drm_init(struct platform_device *pdev)
/* vblank irq init */
ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler,
IRQF_SHARED, dev->driver->name, acrtc);
+
+ INIT_WORK(&acrtc->drm_device_wq, drm_underflow_wq);
+
if (ret)
return ret;