From patchwork Mon May 15 05:54:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99772 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1397199qge; Sun, 14 May 2017 22:55:28 -0700 (PDT) X-Received: by 10.99.3.208 with SMTP id 199mr4375295pgd.43.1494827728852; Sun, 14 May 2017 22:55:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494827728; cv=none; d=google.com; s=arc-20160816; b=iMa8nYBk8Lm/1aSWxNJxiDerP+rXYldvtjTNKaUxgSdvcbHvfLY4AnEJ8tYuwkkJX2 aY5zydPNk8xGi81pLMpVEMF5QI9zQhhYiBP6O6VVKY0xWIvjzqx2XOgp+Om5IfXHqxtA NEplUkjQKl7oqpXDRV461k1ff8f4m/MKTdqmS9ywgZbm/yv/Rd7kUU7rsp1GsKVZwa82 ZrsdE6RmOYo3UXoyuitTrgkwtghjogusPVtPZEdn1a+wOxn/LoHznWBsNPJeA/AJ4L1e ArN1jsFI6IwtJ+gHjNv2260BNB3WvEUr7vgfSShqvfbQcnG7oX6p959YyBkGtlcukDoV FlNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4FCBE8l0k4GVV0QK40T/3dwOs5p9c+YakAAbIFHRVe8=; b=AqyX/H+gMYqkHNrYgx3MXhKg/3Ts+0gp8pRm+o6zgkb9ZocORbsqsJlh2jg6RwLkBR SeVwSo3ehhk30zbYflQSlPpHQynDVU06Tid141iXtOlcqGePlza3AkCmwCvt7cvyqnSL FgXQ4vYpbcpGjGkwF5EJVaz3pIsyeZwLUWO8HZC+dAGlEO3bXo8qPW5hzk03Arktd3Jo fc3Gx0B5dP5hr/xv6VOzUjUEruGQobzUYLfDojL2NWb+zm5kG3W6tYcSMXO3v4dI3f/Z arqPaES67Lo4yv/kTmj5c/IZPdyQwVjBoYu3SbEIuUFAR4cZEl6AyqLtIZDTlV1PAj6o ykVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u5si9784026pfa.19.2017.05.14.22.55.28; Sun, 14 May 2017 22:55:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759402AbdEOFzK (ORCPT + 25 others); Mon, 15 May 2017 01:55:10 -0400 Received: from mail-pg0-f45.google.com ([74.125.83.45]:35128 "EHLO mail-pg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759368AbdEOFzH (ORCPT ); Mon, 15 May 2017 01:55:07 -0400 Received: by mail-pg0-f45.google.com with SMTP id q125so35435920pgq.2 for ; Sun, 14 May 2017 22:55:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4FCBE8l0k4GVV0QK40T/3dwOs5p9c+YakAAbIFHRVe8=; b=VbRG6/1MyOHZGraKY81ZC3eDXA4Is0tmv9sjZ9BtGjCITCQ09cPsAIXsdBPJuTM8+w UslRvuGEIfdoExjcPav0YAUmeiSwDV54CK6pJXjSklArNbkyWJPsW3nBvAWJlC/0Abgm TmCHU6YwiDLKHbfgo74VzWBhlH9gX+T7brrBg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4FCBE8l0k4GVV0QK40T/3dwOs5p9c+YakAAbIFHRVe8=; b=EFnTXlqi/EC0+RUBUBfZ6aqFGFOnv7NphEUOplMisXLDqSuxlIsamuBawz0GH7NTbU qwEHvn+s/tDxx6jC8O8u7kPW50ayXh1Q+CYu75M6qo0Mu13OPVDqr2Igiyxsu+LQIMrw fyMQ/xqpMkBgF3uVbb+R2YgGyum6R58Ox42WrTEL8aK0WhIxfj6UzvtOjfkjpE6uhtjR 4fkMe+r6RJdn+BrKqP+Agc9cI5V6ZrAuRvm30N8AWOGgRS4CY0R0QeKhEWK0GJEK32Qc x1u/DB+pMJ3Nm5m9fRveZDLGRduLQHpF8H2Eug7eNt5Icu3W4ajcuv+RDfz2kxn/laKN ZfIw== X-Gm-Message-State: AODbwcAsh7CRKVj3umqsCapilPo1O1hpqSboi1Xt5tDqFuSmibCo+wr6 KJ/p13zH+I4xsStp X-Received: by 10.98.144.143 with SMTP id q15mr4449493pfk.200.1494827706826; Sun, 14 May 2017 22:55:06 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.87]) by smtp.gmail.com with ESMTPSA id t5sm17315105pgo.48.2017.05.14.22.55.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 14 May 2017 22:55:06 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, guodong.xu@linaro.org, chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Zheng Shaobo Subject: [PATCH 3/3] clk: hi3660: Set PPLL2 to 2880M Date: Mon, 15 May 2017 13:54:23 +0800 Message-Id: <20170515055423.1803-3-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170515055423.1803-1-guodong.xu@linaro.org> References: <20170515055423.1803-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhong Kaihua Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: Zhong Kaihua Signed-off-by: Zheng Shaobo --- drivers/clk/hisilicon/clk-hi3660.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.10.2 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index ffc765a..fd5ce7f 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -20,7 +20,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, }, { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, }, { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, }, - { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 960000000, }, + { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000, }, { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, }, { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, }, { HI3660_PCLK, "pclk", NULL, 0, 20000000, }, @@ -42,7 +42,7 @@ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, }, { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, }, { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, }, - { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 2, 0, }, + { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, }, { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, }, { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, }, { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },