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[209.132.180.67]) by mx.google.com with ESMTP id r3si1477579pgn.278.2017.05.17.01.39.16; Wed, 17 May 2017 01:39:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932111AbdEQIjA (ORCPT + 25 others); Wed, 17 May 2017 04:39:00 -0400 Received: from mail-pg0-f49.google.com ([74.125.83.49]:35019 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932093AbdEQIiw (ORCPT ); Wed, 17 May 2017 04:38:52 -0400 Received: by mail-pg0-f49.google.com with SMTP id q125so3786663pgq.2 for ; Wed, 17 May 2017 01:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CSvqOQ76OxlEcKBZ+wzH3Ianwnym8TM5pp1M1nzBsyc=; b=PTN4Z/sqzCxOM/D5h64zQP7zrIjwxVhIjD6r42LYf1YtFJ8pv6NvPXHa/OfW7PvIiw u3LybnnTpMA38/Zb/km5m/9Gka7SMXSqJu4+4JhP0TXbudji8Bgb9DxGSOhtVdWC+WE4 E6mpevIStCRsU/Ww2rJAQN6z+NDcKA/eVmtdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CSvqOQ76OxlEcKBZ+wzH3Ianwnym8TM5pp1M1nzBsyc=; b=a/af6RNYPdbQHvhnmIebV59YEPwN1bpf5yWQTQBxED8jlfeT6+pGm25UN3W7kIMJfn g63WmxyI1GdapxFr4d5XShgoX3UYP+Np5ROjdUKSZx1LbICXKUqZiO/CvJ+4/kQxkXAj Z5bva3m8IZzr/lGx3YgoP2Oj+Hz2i27Rx5kSSoeCmC28/iGskZ4vYEor02PAKVKCCGyV MnglXyGhMgB8I+SMArFhzeGVg0Aer9Rrj0k/8tK2OjZpYLY031onQssoy0ffvqxAVBRv MYLqQIQGIfzhFMYBCji76UuuS1tOCy3nnBsTfWfqEAmoZSaLwcYTXpRC3H/vPVGEiT85 8uYQ== X-Gm-Message-State: AODbwcAZ4rdMYdfZ8HluxuF5ZRBs1bwJ/lXWtS7VzR/SYNJAZrxuNRtC CuIVZgfIir01wo/8 X-Received: by 10.98.159.135 with SMTP id v7mr2458088pfk.57.1495010327051; Wed, 17 May 2017 01:38:47 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:46 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin , Guodong Xu Subject: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes Date: Wed, 17 May 2017 16:37:40 +0800 Message-Id: <20170517083745.24479-8-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Feng Add nodes uart0 to uart4 and uart6 for hi3660 SoC. Enable uart3 and uart6, disable uart5, in hikey960 board dts. On HiKey960: - UART6 is used as default console, and is wired out through low speed expansion connector. - UART3 has RTS/CTS hardware handshake, and is wired out through low speed expansion connector. - UART5 is not used in commercial launched boards. So disable it. - UART4 is connected to Bluetooth, WL1837. Signed-off-by: Chen Feng Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu Reviewed-by: Zhangfei Gao --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++-- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 60 +++++++++++++++++++++++ 2 files changed, 73 insertions(+), 5 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index f685b1e..513c496 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -15,12 +15,16 @@ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; aliases { - serial5 = &uart5; /* console UART */ + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; }; - chosen { - stdout-path = "serial5:115200n8"; - }; + chosen {}; memory@0 { device_type = "memory"; @@ -47,6 +51,10 @@ status = "okay"; }; -&uart5 { +&uart3 { + status = "okay"; +}; + +&uart6 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3bea0d2..0951a29 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -242,6 +242,56 @@ status = "disabled"; }; + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, + <&crg_ctrl HI3660_CLK_GATE_UART1>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_FACTOR_UART3>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, + <&crg_ctrl HI3660_CLK_GATE_UART4>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; @@ -252,6 +302,16 @@ status = "disabled"; }; + uart6: serial@fff32000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfff32000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_UART6>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + gpio0: gpio@e8a0b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0b000 0 0x1000>;