From patchwork Thu Mar 1 17:49:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liviu Dudau X-Patchwork-Id: 130355 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp3093585edc; Thu, 1 Mar 2018 09:49:24 -0800 (PST) X-Google-Smtp-Source: AG47ELtzJRb5efRzSMbg82ZgPug5uGSiiSADq+B97MryReK40hEYQ2fzKkOG1yEsAb9pZuLpNTTn X-Received: by 2002:a17:902:c81:: with SMTP id 1-v6mr2641870plt.205.1519926564179; Thu, 01 Mar 2018 09:49:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519926564; cv=none; d=google.com; s=arc-20160816; b=owiIYAmChe4IJcY9zCVgB+L8XHQMCModV9F8DxQ5/Uwko2oHrFsZK8V37H7xmKmBm5 KvCPUwtQJbJXzquwMzKKnm27uBuGCu03XtbTgLODSiJKLP/jf8krfAnz+CPGOj61q5Bg tObsnABV4+hEYq0a2AMY9/6J8LZ5ZED9Ka9mpmNafL4Vrb+Tl/V8jRuzcc/eEf0DCKsB jMFD94oZxb5J5k7VPtMNBAjxabvIQGXN9lGp0jsGeobmKvOkQgPzilWK4XYrNvyo2VHO 4vPFerBgpPVsACkZ0Q+5UDwo0Tnu0XYzhpEfWaqTaR8pldwASOBI/CgoujJu2j30Vqs8 9CzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=aQsorC15TMVzors5+bDwVIJ+1lbOaqLdm5gC5TJ1+GA=; b=lQBDsxCt2Md63SMi8AkVMoJt8JeBJG4Yv/XuaR/gx6/VnOWPkasyCT6WLP+tjOT2tl igAhqjWIxlYjQYvOf+QxOWpDZlN82WhShPEl009KPLjD2Ryjpt4h/3Sps2uT/RrdpoMh MmMb3wkz27qLZ9KnRBrVKemTCp4AvgGNke5UJvIeGxnRErADYBqGFKqH85Twp9wamBQX 1i81zapDR//M/zczPTAOt08yNFUyjq+ZpCgkEuYgmNkQcyz+oIqxGA+t+aFUFiL22XfR QT1DUYCbCOl90HlOCAO7icSs09MzC/7gql0M9NGRdiQYXMZ3S4XgFai+pO4wpZLp8KAX QqKQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h12-v6si3405954plt.524.2018.03.01.09.49.23; Thu, 01 Mar 2018 09:49:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1033737AbeCARtU (ORCPT + 28 others); Thu, 1 Mar 2018 12:49:20 -0500 Received: from fw-tnat.cambridge.arm.com ([217.140.96.140]:59740 "EHLO cam-smtp0.cambridge.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1033501AbeCARtS (ORCPT ); Thu, 1 Mar 2018 12:49:18 -0500 Received: from e110455-lin.cambridge.arm.com (e110455-lin.cambridge.arm.com [10.2.131.15]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w21HnDc8015907; Thu, 1 Mar 2018 17:49:13 GMT From: Liviu Dudau To: Brian Starkey Cc: Mali DP Maintainers , Alexandru-Cosmin Gheorghe , DRI devel , LKML , Liviu Dudau Subject: [PATCH v2] drm/mali-dp: Fix malidp_atomic_commit_hw_done() for event sending. Date: Thu, 1 Mar 2018 17:49:13 +0000 Message-Id: <20180301174913.10875-1-Liviu.Dudau@arm.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301173633.9506-1-Liviu.Dudau@arm.com> References: <20180301173633.9506-1-Liviu.Dudau@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Mali DP hardware has a 'go' bit (config_valid) for making the new scene parameters active at the next page flip. The problem with the current code is that the driver first sets this bit and then proceeds to wait for confirmation from the hardware that the configuration has been updated before arming the vblank event. As config_valid is actually asserted by the hardware after the vblank event, during the prefetch phase, when we get to arming the vblank event we are going to send it at the next vblank, in effect halving the vblank rate from the userspace perspective. Fix it by sending the userspace event from the IRQ handler, when we handle the config_valid interrupt, which syncs with the time when the hardware is active with the new parameters. v2: Brian reminded me that interrupts won't fire when CRTC is off, so we need to do the sending ourselves. Cc: Brian Starkey Reported-by: Alexandru-Cosmin Gheorghe Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_drv.c | 30 ++++++++++++++++-------------- drivers/gpu/drm/arm/malidp_drv.h | 1 + drivers/gpu/drm/arm/malidp_hw.c | 12 +++++++++--- 3 files changed, 26 insertions(+), 17 deletions(-) -- 2.16.2 diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index d88a3b9d59cc..a12bef526f92 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -185,25 +185,29 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm) static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state) { - struct drm_pending_vblank_event *event; struct drm_device *drm = state->dev; struct malidp_drm *malidp = drm->dev_private; + malidp->event = malidp->crtc.state->event; + malidp->crtc.state->event = NULL; + if (malidp->crtc.enabled) { + /* + * if we have an event to deliver to userspace, make sure + * the vblank is enabled as we are sending it from the IRQ + * handler. + */ + if (malidp->event) + drm_crtc_vblank_get(&malidp->crtc); + /* only set config_valid if the CRTC is enabled */ - if (malidp_set_and_wait_config_valid(drm)) + if (malidp_set_and_wait_config_valid(drm) < 0) DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n"); - } - - event = malidp->crtc.state->event; - if (event) { - malidp->crtc.state->event = NULL; - + } else if (malidp->event) { + /* CRTC disabled means vblank IRQ is disabled, send event directly */ spin_lock_irq(&drm->event_lock); - if (drm_crtc_vblank_get(&malidp->crtc) == 0) - drm_crtc_arm_vblank_event(&malidp->crtc, event); - else - drm_crtc_send_vblank_event(&malidp->crtc, event); + drm_crtc_send_vblank_event(&malidp->crtc, malidp->event); + malidp->event = NULL; spin_unlock_irq(&drm->event_lock); } drm_atomic_helper_commit_hw_done(state); @@ -232,8 +236,6 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state) malidp_atomic_commit_hw_done(state); - drm_atomic_helper_wait_for_vblanks(drm, state); - pm_runtime_put(drm->dev); drm_atomic_helper_cleanup_planes(drm, state); diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h index e0d12c9fc6b8..c2375bb49619 100644 --- a/drivers/gpu/drm/arm/malidp_drv.h +++ b/drivers/gpu/drm/arm/malidp_drv.h @@ -22,6 +22,7 @@ struct malidp_drm { struct malidp_hw_device *dev; struct drm_crtc crtc; wait_queue_head_t wq; + struct drm_pending_vblank_event *event; atomic_t config_valid; u32 core_id; }; diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 2bfb542135ac..8abd335ec313 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -782,9 +782,15 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) /* first handle the config valid IRQ */ dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS); if (dc_status & hw->map.dc_irq_map.vsync_irq) { - /* we have a page flip event */ - atomic_set(&malidp->config_valid, 1); malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status); + /* do we have a page flip event? */ + if (malidp->event != NULL) { + spin_lock(&drm->event_lock); + drm_crtc_send_vblank_event(&malidp->crtc, malidp->event); + malidp->event = NULL; + spin_unlock(&drm->event_lock); + } + atomic_set(&malidp->config_valid, 1); ret = IRQ_WAKE_THREAD; } @@ -794,7 +800,7 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ); status &= mask; - if (status & de->vsync_irq) + if ((status & de->vsync_irq) && malidp->crtc.enabled) drm_crtc_handle_vblank(&malidp->crtc); malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);