From patchwork Tue Mar 13 12:04:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131449 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp644252ljb; Tue, 13 Mar 2018 05:06:42 -0700 (PDT) X-Google-Smtp-Source: AG47ELtngL4rw8d4HrO493B0kucJqnj3C7VsibeuDiK7VdBppFrwLFBwHohtUYDHyBmrQhx+Imy7 X-Received: by 10.98.89.85 with SMTP id n82mr346344pfb.233.1520942802806; Tue, 13 Mar 2018 05:06:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520942802; cv=none; d=google.com; s=arc-20160816; b=kPlSuRQV8ugizhi+2+DaBPlX27IJZXIhq4scPfgPpYeCVQCbesCQWuYL0h9YH16Gu6 Cs4oi/K9A3NGQjufW3m/q8aXjXUbqBy3hNx45X2Gsxl0dXm72FwpmktuhU6EJFxAatbK WxVbhhUlo0wmsY3B8YwGXvX3MBV8b2wubbvhLYSzkbZC9EvSHVf6aEMdCyiEO14zw0IW pjanDTfN1EliQ6MYnxieR3QW91EmVBShRAkKy6P6yibJbO2XkoyrFkWlW7VFEjsx5x1n DmWgZ9EBTTxYM2SXiiYdjgSBhQHO1a8cJwmHannL0q92JG5IergwnPBUkdlg9o+31GzS xzDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=dBf5+zfEVlq1jtgf5qHc4P3dn9KaBudOM5MLSyfbzuY=; b=W/Qbm3NFuekDgOqKF0+c4oWhxLjUKCVOMxZVeQB+rTwI7rYBe1IPli0ijMZeUGeOK/ uq1HZggG1pc7xhVT9ealfcNVPK4jGuIKsaTiuAs8zYJjEd6IH1XSPpyVahVfN3lQq0K7 G49X/+/YAyzzcIpCjTjMNKCvxmUFyRxFjhCdDqzGhfQNtuf7RRO7SOd3n7mYUiBLJB9i pg9G+bpJLY5Y378Tu3S0QymYYOLsf31t9ClAOUwTKmn5z4Je+SaxQIpvu9g4vOBOi4j7 WiXYF7VZrwIfNZulOpXMSkn5Xa1u0GMOmK3vyhkubT/EE1Ajwj1XvYikVMGQF2XQH703 eKIQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u12si42663pgb.180.2018.03.13.05.06.42; Tue, 13 Mar 2018 05:06:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933388AbeCMMGj (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:55116 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933158AbeCMMGf (ORCPT ); Tue, 13 Mar 2018 08:06:35 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 26950204EF; Tue, 13 Mar 2018 12:06:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 26950204EF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 19/31] perf vendor events arm64: Fixup ThunderX2 to use recommended events Date: Tue, 13 Mar 2018 09:04:56 -0300 Message-Id: <20180313120508.29327-20-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events. Signed-off-by: John Garry Tested-by: Ganapatrao Kulkarni Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-10-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++----------------- 1 file changed, 10 insertions(+), 40 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index 2db45c40ebc7..bc03c06c3918 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -1,62 +1,32 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "L1D_CACHE_RD", }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "L1D_CACHE_WR", }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "L1D_CACHE_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "L1D_TLB_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "L1D_TLB_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "L1D_TLB_RD", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "L1D_TLB_WR", }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "BUS_ACCESS_RD", }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "BUS_ACCESS_WR", } ]