From patchwork Sat Mar 24 13:31:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 132377 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1790158ljb; Sat, 24 Mar 2018 06:33:38 -0700 (PDT) X-Google-Smtp-Source: AG47ELu96SBvcW2Sbf3/X1mPOxA4ZHHKQlRFlPCYXdOWG80B85LYBt8//diXFh2xuR3cII9doWyn X-Received: by 10.98.32.134 with SMTP id m6mr27477719pfj.27.1521898417853; Sat, 24 Mar 2018 06:33:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521898417; cv=none; d=google.com; s=arc-20160816; b=xxNBfXi+xHLmQ8J0UqepC7szjj5DSClSiYGoTvFn2lODxypY3YHqMvvki41otobmvu KbyTpoUmJ3+kqCMBWkXdt9UOcUq2vCjnfGUtIWpE7C6Y1CIbn++UNuZz2BZymoQcpijX BmTpmWgTjyiRMP6l8lcDyOyu+LyUKTx2GjLZMfQBS3Gt3g8E5EHPXj9JcXA4TWJdelTK 7lmqcjs0z6AvkjyZ/6qtRHfmWjWhMwIuem/ioxbTgIKqrJyRKtW3kAhMi2LoQcO5Ozwg A+Z9iTBxzIEnR1ZJjgxocd+mMDlQv1tEPHcvlnJoKV+2qpM6dIpYCldqIo+Fh6G8KxcS z7/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+oJ2fNp/vxnybJEmrB1/1uPVkC+d7Z72pJ0nW2PrRgI=; b=kQUZlcSpsSTKFKKLLpjBdfbywJucidUUp+vfUenHibt39SSTc9jxe9RZOuzfhr7AQv HRnfl8GdhwrYPXULo5LV2n6qQwqegzN1GwijQRyyhuvLA11avOWPYGvK9qM2rle2Hv64 or9Ks8YBDfjRLud6cEi3bCOXjI1R753Oe0ipx9OP0M6qFyosmz292I3gFsbt0n1cIqRG H8YGfC0tpBkVGwB/IUKWe/G5zalxnO5/xU9ONVvkBNvNiVI6mSahzGAHjn4YH3oHihO2 G9lLIui/91Yu6fwyakDNOaRr1Ew5AKdWeg4iyaBrdA7jVOKvWIPSA06HLGGeJ84g2NLY AeMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WMrtpinm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bd7-v6si1634300plb.488.2018.03.24.06.33.37; Sat, 24 Mar 2018 06:33:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WMrtpinm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752412AbeCXNdf (ORCPT + 28 others); Sat, 24 Mar 2018 09:33:35 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34371 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752367AbeCXNdc (ORCPT ); Sat, 24 Mar 2018 09:33:32 -0400 Received: by mail-pf0-f195.google.com with SMTP id j20so5793021pfi.1 for ; Sat, 24 Mar 2018 06:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+oJ2fNp/vxnybJEmrB1/1uPVkC+d7Z72pJ0nW2PrRgI=; b=WMrtpinm2MmXZUyxBBVea8T6MeplRF7yWW7TEPkLATr80dBnvyqwQg4tueCxTC0zaX OlCF40e3U71bsctxQuIsXfIcAnInUdxp4ueemL+OFh+3u/oTbDavIn/Vp6/a/acyNatN /PEZ22bLMlT6NhvxuzXsI+orD/i4OfNsyaKuI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+oJ2fNp/vxnybJEmrB1/1uPVkC+d7Z72pJ0nW2PrRgI=; b=VoeR+xZkyOWsYtDFssm0yu83RwdJ4iSeu9IjqyDpIQ5BMo0oCDCVkZIJTvcZSBMKLP DL3LnHrjw9Tnljmd5FS3isfH78o+5Ko6BX2X+sI6uuojqqcdxA4PyZHdVOFvEe9PPirp 4MhRZ4qoJeguH5VumcVwuPxaDZXhW0SC/eHacLu0zDltibYfY0rG6q6zya4jyPjFHrhH PF983E7jMMSqp5tRk5BAJzVV6PdxIMyho3QIk42TDPNkZo/uZH5BtD7k1nlhaLLiKbxu Pe0Ju9zYBc3fyI5u45bsdA34FYZI1LPT8IwzH8ltBLtffvXkB2bF1hWh7KC3S1sOVRBL cv+A== X-Gm-Message-State: AElRT7EebQhcAt6Lo7+UR7TSBhwx7mRkCshe49VJ583GDHFQHgFE5dgh Tdebq1sRN2xWJexNjZVqy/v2 X-Received: by 10.101.69.198 with SMTP id m6mr22947922pgr.244.1521898412104; Sat, 24 Mar 2018 06:33:32 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7401:11e6:b12d:f551:4edc:7f21]) by smtp.gmail.com with ESMTPSA id a76sm4133980pfc.97.2018.03.24.06.33.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 Mar 2018 06:33:31 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v6 04/11] clk: actions: Add gate clock support Date: Sat, 24 Mar 2018 19:01:52 +0530 Message-Id: <20180324133159.4824-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180324133159.4824-1-manivannan.sadhasivam@linaro.org> References: <20180324133159.4824-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi gate clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-gate.c | 77 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-gate.h | 73 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/clk/actions/owl-gate.c create mode 100644 drivers/clk/actions/owl-gate.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 64a50fc2d335..1f0917872c9d 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o +clk-owl-y += owl-gate.o diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c new file mode 100644 index 000000000000..b87b76e17472 --- /dev/null +++ b/drivers/clk/actions/owl-gate.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL gate clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-gate.h" + +void owl_gate_set(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw, bool enable) +{ + int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + u32 reg; + + set ^= enable; + + regmap_read(common->regmap, gate_hw->reg, ®); + + if (set) + reg |= BIT(gate_hw->bit_idx); + else + reg &= ~BIT(gate_hw->bit_idx); + + regmap_write(common->regmap, gate_hw->reg, reg); +} + +static void owl_gate_disable(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + owl_gate_set(common, &gate->gate_hw, false); +} + +static int owl_gate_enable(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + owl_gate_set(common, &gate->gate_hw, true); + + return 0; +} + +int owl_clk_is_enabled(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw) +{ + u32 reg; + + regmap_read(common->regmap, gate_hw->reg, ®); + + if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE) + reg ^= BIT(gate_hw->bit_idx); + + return !!(reg & BIT(gate_hw->bit_idx)); +} + +static int owl_gate_is_enabled(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + return owl_clk_is_enabled(common, &gate->gate_hw); +} + +const struct clk_ops owl_gate_ops = { + .disable = owl_gate_disable, + .enable = owl_gate_enable, + .is_enabled = owl_gate_is_enabled, +}; diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h new file mode 100644 index 000000000000..f37b33a1be6b --- /dev/null +++ b/drivers/clk/actions/owl-gate.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL gate clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_GATE_H_ +#define _OWL_GATE_H_ + +#include "owl-common.h" + +struct owl_gate_hw { + u32 reg; + u8 bit_idx; + u8 gate_flags; +}; + +struct owl_gate { + struct owl_gate_hw gate_hw; + struct owl_clk_common common; +}; + +#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ + { \ + .reg = _reg, \ + .bit_idx = _bit_idx, \ + .gate_flags = _gate_flags, \ + } + +#define OWL_GATE(_struct, _name, _parent, _reg, \ + _bit_idx, _gate_flags, _flags) \ + struct owl_gate _struct = { \ + .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_gate_ops, \ + _flags), \ + } \ + } \ + +#define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ + _bit_idx, _gate_flags, _flags) \ + struct owl_gate _struct = { \ + .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ + &owl_gate_ops, \ + _flags), \ + }, \ + } \ + +static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_gate, common); +} + +void owl_gate_set(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw, bool enable); +int owl_gate_is_enabled(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw); + +extern const struct clk_ops owl_gate_ops; + +#endif /* _OWL_GATE_H_ */