From patchwork Fri Mar 22 08:58:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 160882 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp557509jan; Fri, 22 Mar 2019 01:58:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqwLc5uBTPr9VWgbm7VN1P7G+H7yqRgAD2+zQ2EwSIaM/BjOgnOUaooFkwD2JcwUVBreOrrt X-Received: by 2002:a17:902:76c1:: with SMTP id j1mr6760277plt.224.1553245105464; Fri, 22 Mar 2019 01:58:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553245105; cv=none; d=google.com; s=arc-20160816; b=YA8GybzGdDOJjo1noBXuzEcH90/wIlQl6AjTg3aLzjItiAtcJ9/7zFjP5vhcZNisrR tZmP9cMFXImmYOiq1t21AgIGx5MhPC0pEUQxGRw/Lj8g279wwLZd7A/9noeDMKyljlOD alspnmxYk/+WDFYSRyIeNw/BOWj8zY9h488OFy5YEv0HRV0MabMX+zWRXxGgNCESzcm0 bSpalm4bSVTSDuJUXBC/YVAp4atIClrR/VY68li/3oniwV095NjX0YmvJlUsUx9m6vKE En8z5p3Uz1Ez//pAGnkP3I85+VcWlYiVWuLwOzWdfam9d+QMY5Z0TVHKsoE6grTXa3HM Erqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WYQ3YkHVR4l79yltClpUWyBrd1XOrHVgrBA+RFSZlWw=; b=GJt4/lY8FYh+rIbqKrBsctCok7o9B8y4zwpoo64sgEb36phZb/snJsFTVb8LPHH14s vy+GwK16m5eIfMcWaz+vt9w8xLFyn1HJqWKVLi3JwwvO4TtpLaAjy9HQQG/zJERvd4tX OnuC4pHjiR4Oy9WqphS+4ABcdvmPvtt5PAjiBers4ei3Gdt8x/56fjapfghlJ2YIJs8V J7D2iIKDM76ocPgqhHAWYLMf3FhpbPPxP723j3nocJNKXW7/YXaVqIQs4TQetkycp7CX wLhI6C+qjyaO7dAa9Z9l8sFFcUzihpehAp6XFUxxM5c33+CeZcsv5IkK4mpKJeqXuC+R Cl0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=U0BTqqzZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v198si3827557pgb.204.2019.03.22.01.58.25; Fri, 22 Mar 2019 01:58:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=U0BTqqzZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727918AbfCVI6X (ORCPT + 31 others); Fri, 22 Mar 2019 04:58:23 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:52124 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727884AbfCVI6V (ORCPT ); Fri, 22 Mar 2019 04:58:21 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2M8wLd7071009 for ; Fri, 22 Mar 2019 03:58:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553245101; bh=WYQ3YkHVR4l79yltClpUWyBrd1XOrHVgrBA+RFSZlWw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=U0BTqqzZvW1OKxoyICXuUreYAbIEUYqv4LOlfRdvQhc0HSabMjlO0IaHtM6XQpQhI bGOAWqEN6olG6eBNl2AGn7PpEkMs01tTxLB2du/69uxN6whhhybG6xLAlSuCTGe2pB AfTTvp+NNUtAqkF+cjz9gLei0BUdPvTQC8EMGh6I= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2M8wLX1065817 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Fri, 22 Mar 2019 03:58:21 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 22 Mar 2019 03:58:18 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Fri, 22 Mar 2019 03:58:18 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2M8w9bA016866; Fri, 22 Mar 2019 03:58:16 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [PATCH 4/4] phy: ti-pipe3: Fix PCIe power up sequence Date: Fri, 22 Mar 2019 10:58:07 +0200 Message-ID: <20190322085807.30216-5-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190322085807.30216-1-rogerq@ti.com> References: <20190322085807.30216-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TRM [1] mentions that we need to power up PCIESS_PHY_TX and PCIESS_PHY_RX before configuring PCIe_PHY_RX SCP settings. See "Table 26-81. PCIePHY Subsystem Low-Level Programming Sequence". [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-ti-pipe3.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 71a7634c026d..1718ef36d290 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -341,6 +341,8 @@ static int ti_pipe3_power_off(struct phy *x) return ret; } +static void ti_pipe3_calibrate(struct ti_pipe3 *phy); + static int ti_pipe3_power_on(struct phy *x) { u32 val; @@ -386,6 +388,9 @@ static int ti_pipe3_power_on(struct phy *x) mask, val); } + if (phy->mode == PIPE3_MODE_PCIE) + ti_pipe3_calibrate(phy); + return 0; } @@ -520,12 +525,7 @@ static int ti_pipe3_init(struct phy *x) val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, PCIE_PCS_MASK, val); - if (ret) - return ret; - - ti_pipe3_calibrate(phy); - - return 0; + return ret; } /* Bring it out of IDLE if it is IDLE */