From patchwork Wed Jul 24 16:25:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169622 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp10466340ilk; Wed, 24 Jul 2019 09:25:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqz1M+AGAjGSNDyHCztvcekc8YmZ5MTTdCAJ+7ljgyhzOLzbrG9bAf3Z69QUELyDnomzuajt X-Received: by 2002:a17:902:5ac4:: with SMTP id g4mr88618992plm.80.1563985556954; Wed, 24 Jul 2019 09:25:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563985556; cv=none; d=google.com; s=arc-20160816; b=T39QJ0xSaIWc0qJFymUv7MeBpZqD4ZIltXhV9PXuO/nqa1RGXFfCDKvZl3Elmhkg5W XSCVcQRIU8t82feky2x+krTjrELwyx7/6exuztC2U8u8o4FUy8ab7N443AN70xwcplGL EoJdgzIEwtRnPMYUow4JT7r13INEWmBaR4BzASM6LWzx1C5iCIJdmf07u2Y723Fk/EWL KhWFG5doiQHaGly/3dWjq0xogHo0ck2C1fzHppcn23KQgx2+F3rnxPzwZ8HMCHo6uXu+ 05rDak4oM3ALCS6gvfjwQd/ZbfVruuF7+u5p4ibcrKwOhg/YJ2q/6wHFROso24LBoiGD 7cWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Xd7v8bSn1XNVtCYUofIUeCtELes/ht1XTsRDsKyb3h0=; b=nQ9+W9bNnbKZEJYwaYasCbYvIdW4HOR3HDmT5hnmI7ZOMt64rm9vankF42bdMa9g0m Tft4d5t/mJICilHSvntRZZOoVdvhsEbCdZJ/qYJVx+uphPvQAeAW2ciABuCgp61jDrvN BAJlOKzQGvoBP+MKKZbjkb/pt9AaREu83zFZ2sAoo/hN4VS4j2dhxmnFLuGLuCLGlrzQ Tan73w8f+odQduiltC7fgSq6VCU7vNJCHYjDAK+rgDrVcqO3uEcefRdGS2Zd7omQGEU0 L0XkMzNjzhmhc1Z7j95nnKPicAgClGnzkljXxO1cQQQ7JoeHs67H4s7Xmj2aUtYmzVdZ wd4A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l63si15941264pfl.41.2019.07.24.09.25.56; Wed, 24 Jul 2019 09:25:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728856AbfGXQZz (ORCPT + 29 others); Wed, 24 Jul 2019 12:25:55 -0400 Received: from foss.arm.com ([217.140.110.172]:43366 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728789AbfGXQZy (ORCPT ); Wed, 24 Jul 2019 12:25:54 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 691CE28; Wed, 24 Jul 2019 09:25:53 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 156643F71F; Wed, 24 Jul 2019 09:25:51 -0700 (PDT) From: Julien Grall To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: james.morse@arm.com, marc.zyngier@arm.com, julien.thierry@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Grall Subject: [PATCH v3 04/15] arm64/mm: Move the variable lock and tlb_flush_pending to asid_info Date: Wed, 24 Jul 2019 17:25:23 +0100 Message-Id: <20190724162534.7390-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190724162534.7390-1-julien.grall@arm.com> References: <20190724162534.7390-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The variables lock and tlb_flush_pending holds information for a given ASID allocator. So move them to the asid_info structure. Signed-off-by: Julien Grall --- arch/arm64/mm/context.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.11.0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 49fff350e12f..b50f52a09baf 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -16,8 +16,6 @@ #include #include -static DEFINE_RAW_SPINLOCK(cpu_asid_lock); - static struct asid_info { atomic64_t generation; @@ -25,6 +23,9 @@ static struct asid_info atomic64_t __percpu *active; u64 __percpu *reserved; u32 bits; + raw_spinlock_t lock; + /* Which CPU requires context flush on next call */ + cpumask_t flush_pending; } asid_info; #define active_asid(info, cpu) *per_cpu_ptr((info)->active, cpu) @@ -33,8 +34,6 @@ static struct asid_info static DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); -static cpumask_t tlb_flush_pending; - #define ASID_MASK(info) (~GENMASK((info)->bits - 1, 0)) #define ASID_FIRST_VERSION(info) (1UL << ((info)->bits)) @@ -113,7 +112,7 @@ static void flush_context(struct asid_info *info) * Queue a TLB invalidation for each CPU to perform on next * context-switch */ - cpumask_setall(&tlb_flush_pending); + cpumask_setall(&info->flush_pending); } static bool check_update_reserved_asid(struct asid_info *info, u64 asid, @@ -222,7 +221,7 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) old_active_asid, asid)) goto switch_mm_fastpath; - raw_spin_lock_irqsave(&cpu_asid_lock, flags); + raw_spin_lock_irqsave(&info->lock, flags); /* Check that our ASID belongs to the current generation. */ asid = atomic64_read(&mm->context.id); if ((asid ^ atomic64_read(&info->generation)) >> info->bits) { @@ -230,11 +229,11 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) atomic64_set(&mm->context.id, asid); } - if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) + if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending)) local_flush_tlb_all(); atomic64_set(&active_asid(info, cpu), asid); - raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); + raw_spin_unlock_irqrestore(&info->lock, flags); switch_mm_fastpath: @@ -277,6 +276,8 @@ static int asids_init(void) info->active = &active_asids; info->reserved = &reserved_asids; + raw_spin_lock_init(&info->lock); + pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS(info)); return 0;