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[209.132.180.67]) by mx.google.com with ESMTP id k91-v6si1095884pld.361.2018.02.28.02.48.08; Wed, 28 Feb 2018 02:48:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kd5o/r85; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932124AbeB1KsD (ORCPT + 28 others); Wed, 28 Feb 2018 05:48:03 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:45250 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752571AbeB1KsA (ORCPT ); Wed, 28 Feb 2018 05:48:00 -0500 Received: by mail-pf0-f196.google.com with SMTP id j24so828455pff.12 for ; Wed, 28 Feb 2018 02:48:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=4HxcZH0DtV4NcaXnZLkC43Ia5hO1UX3XhfgQAp7Y+rk=; b=Kd5o/r85Y5cag7QvQFNngyMMFIQHXfSrg9ogqzBQdtT2sbX/+OKHplGRJ9UOU+UdQu j1Y3SrkRWON0zDqxM4SXhvBsBTfLgw/nMA3jBHqozNSBxQNlZidEb0eXtqrXFKQxT9g4 qc9lG1vni9CeOYZcno93Cvwhh6KBnJNouAsFs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=4HxcZH0DtV4NcaXnZLkC43Ia5hO1UX3XhfgQAp7Y+rk=; b=gjV5GZB9CXd2JYDPdiw2ySFFI5S0V1ltNflDRCdV3UpPuwV9ncg64RssL4WjNfjDq0 s9pzWu5OIppOKrqYIlnOt7LE7KxSKdMJmtPKJ6yKIDbn3w9Hsyl8EoePy3y+7MOpPI5o MJWxiAXNa2butAu7JnPPCpn/OIWC7ySJfsVYK9nb4PBMpMdegf56lhVsMhNrcHFMeKnv 3oPt6VFflmDzwYydZdgGbVMJ0Bo8ojwnqYlIsWnTRHfUSxfTA7ggdO3DqU723W59CESf +BAJQ4ZUs7NcvyK5638APheKE3bj5haae4ofNwFSxBTEHfmGwIQEv7LiM74r2hJCrc+s 00Qw== X-Gm-Message-State: APf1xPD9v8iY1mLDvgRitwf+oE9RwsAQJN1fCw4VX+eUAzBc3ygU75NH hCsIcPmdJUwyiBkj5Ywz0w+rAg== X-Received: by 10.98.153.157 with SMTP id t29mr17430909pfk.201.1519814879954; Wed, 28 Feb 2018 02:47:59 -0800 (PST) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id v14sm3636129pfi.8.2018.02.28.02.47.56 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 02:47:59 -0800 (PST) From: Baolin Wang To: robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, arnd@arndb.de Cc: chunyan.zhang@linaro.org, orson.zhai@spreadtrum.com, mathieu.poirier@linaro.org, devicetree@vger.kernel.org, arm@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, broonie@kernel.org, baolin.wang@linaro.org Subject: [RESEND PATCH 3/7] arm64: dts: Add pin controller node for Spreadtrum SC9860 Date: Wed, 28 Feb 2018 18:47:06 +0800 Message-Id: <378c75289917a9686814f2870752f953977f564c.1519814593.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <5ec790b43c6fea9f36e06b5b20233b2adebd7d50.1519814593.git.baolin.wang@linaro.org> References: <5ec790b43c6fea9f36e06b5b20233b2adebd7d50.1519814593.git.baolin.wang@linaro.org> In-Reply-To: <5ec790b43c6fea9f36e06b5b20233b2adebd7d50.1519814593.git.baolin.wang@linaro.org> References: <5ec790b43c6fea9f36e06b5b20233b2adebd7d50.1519814593.git.baolin.wang@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the pin controller device node for Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang --- arch/arm64/boot/dts/sprd/whale2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 1.7.9.5 diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 63fe89e..23cedbd 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -129,6 +129,11 @@ clock-names = "enable"; clocks = <&aon_gate CLK_SPLK_EB>; }; + + pin_controller: pinctrl@402a0000 { + compatible = "sprd,sc9860-pinctrl"; + reg = <0 0x402a0000 0 0x10000>; + }; }; };