From patchwork Mon Nov 4 02:47:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "kernelci.org bot" X-Patchwork-Id: 178386 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp896707ilf; Sun, 3 Nov 2019 18:47:54 -0800 (PST) X-Google-Smtp-Source: APXvYqxTrLHPew7lQuNxg78952Egy5UcfFTIeT/Lba6py4qP3W2t9ifePMqyOR4W9XvSglGvcFJP X-Received: by 2002:a17:906:bfc6:: with SMTP id us6mr21815228ejb.51.1572835674720; Sun, 03 Nov 2019 18:47:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572835674; cv=none; d=google.com; s=arc-20160816; b=ZPU+ZtbDgK4ZWlWcLi7GVkyrMUR8AUmf8r1BaOc4lAkkVlxvn17D2/6JjhzWKV+OXK 6HmtjtbhqCmuE7v32bQ6sc/tUj5A9x6omKe2I88TOPOXSMZQGP0CAQtCJHj5TYiFjaLb TIUmPl1SHdW8ykFePC/o6Fcd1255yGqPwczAQM5n14rFL0dgbiaUGcevlR7n8YC9sKvR 8uoW7Bhc3gLh+phQzzBMeKcus9KG+JNshAzKJBXgQf7BTgj6LbpTR3Hi+Kv5ToOxdkbk pjPNLfSvTKOZ39xaQ4NyDb2NWLZMCfoNv0uTDJ/Dl7+eM/c3SC3kFzTTx3pPbgNmvE3g Zx8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:from:to:subject :content-transfer-encoding:mime-version:date:message-id :dkim-signature; bh=9cGr+26SuuP7VEqqq+GDz6d2bR5jxl9oMBAlWYPVZps=; b=bgz1UlvqUGMp9kTykDqEVTFbE7SDz85NZJC0o+WJGou2ebaC4DwE15KFChSBwUggLa XP5q/hV5Pp2E9qd8Z3QOeUGJ38LIDpGr8HUTaSrHSiKBNKy0E07/cr60O0JQyBpzxu7h WvtAaX0K0pge6EXIBHci5dLa16B7J6vzvxhkO303nCCotlTEckW64X8q35w/8fkCjhFy C4kFKVzaMISoRZnDEvLtDbBR6ALHZHUHdBI3yX5Wa9gEcPMmXNeDGPZMxkbUpldYkxji OP7A0s8a/quy3FPOI4Y7I3YVbMFfrLn2z8UKiK+V8GMfYTjMZtKwes9nYSWk7lIP4nla iFIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernelci-org.20150623.gappssmtp.com header.s=20150623 header.b=ppstoFT9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d10si7130225edk.122.2019.11.03.18.47.54; Sun, 03 Nov 2019 18:47:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernelci-org.20150623.gappssmtp.com header.s=20150623 header.b=ppstoFT9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729107AbfKDCrr (ORCPT + 26 others); Sun, 3 Nov 2019 21:47:47 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:36864 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729045AbfKDCrq (ORCPT ); Sun, 3 Nov 2019 21:47:46 -0500 Received: by mail-wm1-f67.google.com with SMTP id q130so14413798wme.2 for ; Sun, 03 Nov 2019 18:47:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernelci-org.20150623.gappssmtp.com; s=20150623; h=message-id:date:mime-version:content-transfer-encoding:subject:to :from:cc; bh=9cGr+26SuuP7VEqqq+GDz6d2bR5jxl9oMBAlWYPVZps=; b=ppstoFT91rOslY1m9gVim95v5fAi6rqhPJqPWF8OXarce/jvFEerfVH8vdUbY42GaC XAtMpecI/wW0qp9jheosmCdTZl7FeU0d3l++qJdHpLN7G0GEG7Uu+MxmHVyCIva9mOjD a0EgLKPBwEVpuxrBhzR9WcGsKbvZOVjoRW5SH+nj+jnRTxWbr8nHTxaRaDG+0xMW46+m dKlx4bK+WIeY1zH0Bm4l/2+XFHV4EXSAGzqmvk5uM4qNiqJq9PG2I5YLFy6DgYnHdsJf jbMWN8oD8vPZrftwkDmy3cfXvcl6svYpcAj3jgRDiyfVk0AGA6L8koIv6YzKx1ueoADg 6RvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:date:mime-version :content-transfer-encoding:subject:to:from:cc; bh=9cGr+26SuuP7VEqqq+GDz6d2bR5jxl9oMBAlWYPVZps=; b=rDNPHnBxX1cmVjp9bVN2yQ4JLv/iOi2rqfpMdG8NvRZwic4//rFkWouGLHrh7wEpWE B3PrJ4HqY0zfcUiLXNTa0+qYtJ7ZeY0BzvkOr1H4ns/4QhhrpVc3sJMtHAv2UZRfMSpA wasrzyEqIa7MNhx5atdB63MhkpHRiHTgtm8PMn7nyKHOiRBX8jA4V2VI6xEqQb77o465 M1top0MbLxNmph0Qb4QGuT4M1WB1mY1431NwF1upiuxI7sPedpSTxl6i0s6Yyl7vKX+N tMUD5C53U6BqLW9iGLMXxwlbOlJGkMFmSXfS7FqkcxTeY7KPGLg7zhy9KOgvabQCDppC LX9Q== X-Gm-Message-State: APjAAAU5k3S0IheFuDz3qqJj3UOrMAw3eoEJXnfyaMFz5Vf9LoOUMNjx bfxMoOGWvNio3zRIiNq7aPB92Q== X-Received: by 2002:a7b:c748:: with SMTP id w8mr17748710wmk.114.1572835661547; Sun, 03 Nov 2019 18:47:41 -0800 (PST) Received: from [148.251.42.114] ([2a01:4f8:201:9271::2]) by smtp.gmail.com with ESMTPSA id j11sm11125108wrq.26.2019.11.03.18.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2019 18:47:40 -0800 (PST) Message-ID: <5dbf914c.1c69fb81.2e378.d927@mx.google.com> Date: Sun, 03 Nov 2019 18:47:40 -0800 (PST) MIME-Version: 1.0 X-Kernelci-Branch: for-next X-Kernelci-Lab-Name: lab-baylibre X-Kernelci-Tree: linusw X-Kernelci-Report-Type: bisect X-Kernelci-Kernel: v5.4-rc4-34-gb0983a8bbfb4 Subject: linusw/for-next boot bisection: v5.4-rc4-34-gb0983a8bbfb4 on r8a7795-salvator-x To: Linus Walleij , tomeu.vizoso@collabora.com, guillaume.tucker@collabora.com, mgalka@collabora.com, broonie@kernel.org, matthew.hart@linaro.org, Scott Branden , khilman@baylibre.com, enric.balletbo@collabora.com, Chris Packham From: "kernelci.org bot" Cc: Scott Branden , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Bartosz Golaszewski , Ray Jui , linux-arm-kernel@lists.infradead.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This automated bisection report was sent to you on the basis * * that you may be involved with the breaking commit it has * * found. No manual investigation has been done to verify it, * * and the root cause of the problem may be somewhere else. * * * * If you do send a fix, please include this trailer: * * Reported-by: "kernelci.org bot" * * * * Hope this helps! * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * linusw/for-next boot bisection: v5.4-rc4-34-gb0983a8bbfb4 on r8a7795-salvator-x Summary: Start: b0983a8bbfb4 Merge branch 'devel' into for-next Details: https://kernelci.org/boot/id/5dbf677159b514c28c138dfe Plain log: https://storage.kernelci.org//linusw/for-next/v5.4-rc4-34-gb0983a8bbfb4/arm64/defconfig/gcc-8/lab-baylibre/boot-r8a7795-salvator-x.txt HTML log: https://storage.kernelci.org//linusw/for-next/v5.4-rc4-34-gb0983a8bbfb4/arm64/defconfig/gcc-8/lab-baylibre/boot-r8a7795-salvator-x.html Result: 6a41b6c5fc20 gpio: Add xgs-iproc driver Checks: revert: PASS verify: PASS Parameters: Tree: linusw URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/ Branch: for-next Target: r8a7795-salvator-x CPU arch: arm64 Lab: lab-baylibre Compiler: gcc-8 Config: defconfig Test suite: boot Breaking commit found: ------------------------------------------------------------------------------- commit 6a41b6c5fc20abced88fa0eed42ae5e5cb70b280 Author: Chris Packham Date: Fri Oct 25 09:27:03 2019 +1300 gpio: Add xgs-iproc driver This driver supports the Chip Common A GPIO controller present on a number of Broadcom switch ASICs with integrated SoCs. The controller is similar to the pinctrl-nsp-gpio and pinctrl-iproc-gpio blocks but different enough that a separate driver is required. This has been ported from Broadcom's XLDK 5.0.3 retaining only the CCA support (pinctrl-iproc-gpio covers CCB). Signed-off-by: Chris Packham Link: https://lore.kernel.org/r/20191024202703.8017-3-chris.packham@alliedtelesis.co.nz Acked-by: Scott Branden Signed-off-by: Linus Walleij ------------------------------------------------------------------------------- Git bisection log: ------------------------------------------------------------------------------- git bisect start # good: [7d194c2100ad2a6dded545887d02754948ca5241] Linux 5.4-rc4 git bisect good 7d194c2100ad2a6dded545887d02754948ca5241 # bad: [b0983a8bbfb45d16760b34c23436a3d9b5834dbf] Merge branch 'devel' into for-next git bisect bad b0983a8bbfb45d16760b34c23436a3d9b5834dbf # good: [698b8eeaed7287970fc2b6d322618850fd1b1e6c] gpio/mpc8xxx: change irq handler from chained to normal git bisect good 698b8eeaed7287970fc2b6d322618850fd1b1e6c # good: [ac4062aa6c811db89ee3bbfd3101af931a50c1ba] gpio: 104-idi-48e: make array register_offset static, makes object smaller git bisect good ac4062aa6c811db89ee3bbfd3101af931a50c1ba # good: [d57eb825e0dc6f0b5be78251d69cbf1bdd1db622] gpio: Add RDA Micro GPIO controller support git bisect good d57eb825e0dc6f0b5be78251d69cbf1bdd1db622 # bad: [6a41b6c5fc20abced88fa0eed42ae5e5cb70b280] gpio: Add xgs-iproc driver git bisect bad 6a41b6c5fc20abced88fa0eed42ae5e5cb70b280 # good: [1dfc462a54386d8467ff427ef900f553e2e470e3] dt-bindings: gpio: brcm: Add bindings for xgs-iproc git bisect good 1dfc462a54386d8467ff427ef900f553e2e470e3 # first bad commit: [6a41b6c5fc20abced88fa0eed42ae5e5cb70b280] gpio: Add xgs-iproc driver ------------------------------------------------------------------------------- diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8ec1f041c98d..e9516393c971 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -155,6 +155,15 @@ config GPIO_BCM_KONA help Turn on GPIO support for Broadcom "Kona" chips. +config GPIO_BCM_XGS_IPROC + tristate "BRCM XGS iProc GPIO support" + depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + default ARCH_BCM_IPROC + help + Say yes here to enable GPIO support for Broadcom XGS iProc SoCs. + config GPIO_BRCMSTB tristate "BRCMSTB GPIO support" default y if (ARCH_BRCMSTB || BMIPS_GENERIC) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 84e05701f500..34eb8b2b12dd 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o +obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o diff --git a/drivers/gpio/gpio-xgs-iproc.c b/drivers/gpio/gpio-xgs-iproc.c new file mode 100644 index 000000000000..a3fdd95cc9e6 --- /dev/null +++ b/drivers/gpio/gpio-xgs-iproc.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Broadcom + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IPROC_CCA_INT_F_GPIOINT BIT(0) +#define IPROC_CCA_INT_STS 0x20 +#define IPROC_CCA_INT_MASK 0x24 + +#define IPROC_GPIO_CCA_DIN 0x0 +#define IPROC_GPIO_CCA_DOUT 0x4 +#define IPROC_GPIO_CCA_OUT_EN 0x8 +#define IPROC_GPIO_CCA_INT_LEVEL 0x10 +#define IPROC_GPIO_CCA_INT_LEVEL_MASK 0x14 +#define IPROC_GPIO_CCA_INT_EVENT 0x18 +#define IPROC_GPIO_CCA_INT_EVENT_MASK 0x1C +#define IPROC_GPIO_CCA_INT_EDGE 0x24 + +struct iproc_gpio_chip { + struct irq_chip irqchip; + struct gpio_chip gc; + spinlock_t lock; + struct device *dev; + void __iomem *base; + void __iomem *intr; +}; + +static inline struct iproc_gpio_chip * +to_iproc_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct iproc_gpio_chip, gc); +} + +static void iproc_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 irq_type, event_status = 0; + + spin_lock_irqsave(&chip->lock, flags); + irq_type = irq_get_trigger_type(irq); + if (irq_type & IRQ_TYPE_EDGE_BOTH) { + event_status |= BIT(pin); + writel_relaxed(event_status, + chip->base + IPROC_GPIO_CCA_INT_EVENT); + } + spin_unlock_irqrestore(&chip->lock, flags); +} + +static void iproc_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 int_mask, irq_type, event_mask; + + spin_lock_irqsave(&chip->lock, flags); + irq_type = irq_get_trigger_type(irq); + event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) { + event_mask |= 1 << pin; + writel_relaxed(event_mask, + chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + } else { + int_mask |= 1 << pin; + writel_relaxed(int_mask, + chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + } + spin_unlock_irqrestore(&chip->lock, flags); +} + +static void iproc_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 irq_type, int_mask, event_mask; + + spin_lock_irqsave(&chip->lock, flags); + irq_type = irq_get_trigger_type(irq); + event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + + if (irq_type & IRQ_TYPE_EDGE_BOTH) { + event_mask &= ~BIT(pin); + writel_relaxed(event_mask, + chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + } else { + int_mask &= ~BIT(pin); + writel_relaxed(int_mask, + chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + } + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int iproc_gpio_irq_set_type(struct irq_data *d, u32 type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int pin = d->hwirq; + unsigned long flags; + u32 irq = d->irq; + u32 event_pol, int_pol; + int ret = 0; + + spin_lock_irqsave(&chip->lock, flags); + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE); + event_pol &= ~BIT(pin); + writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE); + break; + case IRQ_TYPE_EDGE_FALLING: + event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE); + event_pol |= BIT(pin); + writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE); + break; + case IRQ_TYPE_LEVEL_HIGH: + int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); + int_pol &= ~BIT(pin); + writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL); + break; + case IRQ_TYPE_LEVEL_LOW: + int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); + int_pol |= BIT(pin); + writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL); + break; + default: + /* should not come here */ + ret = -EINVAL; + goto out_unlock; + } + + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(irq_get_irq_data(irq), handle_level_irq); + else if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(irq_get_irq_data(irq), handle_edge_irq); + +out_unlock: + spin_unlock_irqrestore(&chip->lock, flags); + + return ret; +} + +static irqreturn_t iproc_gpio_irq_handler(int irq, void *data) +{ + struct gpio_chip *gc = (struct gpio_chip *)data; + struct iproc_gpio_chip *chip = to_iproc_gpio(gc); + int bit; + unsigned long int_bits = 0; + u32 int_status; + + /* go through the entire GPIOs and handle all interrupts */ + int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS); + if (int_status & IPROC_CCA_INT_F_GPIOINT) { + u32 event, level; + + /* Get level and edge interrupts */ + event = + readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); + event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT); + level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN); + level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); + level &= + readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); + int_bits = level | event; + + for_each_set_bit(bit, &int_bits, gc->ngpio) + generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit)); + } + + return int_bits ? IRQ_HANDLED : IRQ_NONE; +} + +static int iproc_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *dn = pdev->dev.of_node; + struct iproc_gpio_chip *chip; + u32 num_gpios; + int irq, ret; + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = dev; + platform_set_drvdata(pdev, chip); + spin_lock_init(&chip->lock); + + chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + + ret = bgpio_init(&chip->gc, dev, 4, + chip->base + IPROC_GPIO_CCA_DIN, + chip->base + IPROC_GPIO_CCA_DOUT, + NULL, + chip->base + IPROC_GPIO_CCA_OUT_EN, + NULL, + 0); + if (ret) { + dev_err(dev, "unable to init GPIO chip\n"); + return ret; + } + + chip->gc.label = dev_name(dev); + if (of_property_read_u32(dn, "ngpios", &num_gpios)) + chip->gc.ngpio = num_gpios; + + irq = platform_get_irq(pdev, 0); + if (irq > 0) { + struct gpio_irq_chip *girq; + struct irq_chip *irqc; + u32 val; + + irqc = &chip->irqchip; + irqc->name = dev_name(dev); + irqc->irq_ack = iproc_gpio_irq_ack; + irqc->irq_mask = iproc_gpio_irq_mask; + irqc->irq_unmask = iproc_gpio_irq_unmask; + irqc->irq_set_type = iproc_gpio_irq_set_type; + + chip->intr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->intr)) + return PTR_ERR(chip->intr); + + /* Enable GPIO interrupts for CCA GPIO */ + val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK); + val |= IPROC_CCA_INT_F_GPIOINT; + writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK); + + /* + * Directly request the irq here instead of passing + * a flow-handler to gpiochip_set_chained_irqchip, + * because the irq is shared. + */ + ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler, + IRQF_SHARED, chip->gc.label, &chip->gc); + if (ret) { + dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret); + return ret; + } + + girq = &chip->gc.irq; + girq->chip = irqc; + /* This will let us handle the parent IRQ in the driver */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + } + + ret = devm_gpiochip_add_data(dev, &chip->gc, chip); + if (ret) { + dev_err(dev, "unable to add GPIO chip\n"); + return ret; + } + + return 0; +} + +static int __exit iproc_gpio_remove(struct platform_device *pdev) +{ + struct iproc_gpio_chip *chip; + + chip = platform_get_drvdata(pdev); + if (!chip) + return -ENODEV; + + if (chip->intr) { + u32 val; + + val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK); + val &= ~IPROC_CCA_INT_F_GPIOINT; + writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK); + } + + return 0; +} + +static const struct of_device_id bcm_iproc_gpio_of_match[] __initconst = { + { .compatible = "brcm,iproc-gpio-cca" }, + {} +}; +MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match); + +static struct platform_driver bcm_iproc_gpio_driver = { + .driver = { + .name = "iproc-xgs-gpio", + .owner = THIS_MODULE, + .of_match_table = bcm_iproc_gpio_of_match, + }, + .probe = iproc_gpio_probe, + .remove = iproc_gpio_remove, +}; + +module_platform_driver(bcm_iproc_gpio_driver); + +MODULE_DESCRIPTION("XGS IPROC GPIO driver"); +MODULE_LICENSE("GPL v2");