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[209.132.180.67]) by mx.google.com with ESMTP id 1si12801477pgk.12.2017.05.16.00.54.32; Tue, 16 May 2017 00:54:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751653AbdEPHy3 (ORCPT + 25 others); Tue, 16 May 2017 03:54:29 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:33827 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751488AbdEPHy1 (ORCPT ); Tue, 16 May 2017 03:54:27 -0400 Received: by mail-pg0-f52.google.com with SMTP id u28so72543985pgn.1 for ; Tue, 16 May 2017 00:54:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=N67Zp1XY4qKa3NxJa5bBoyNpr/K4YmTSy5pefYnl2/g=; b=DRZ3ZaVsgUJMas+s0Dtmxn0++VKcneLQynQlD1qPnOOBPQWm+6oYKj9SqCP1MOz4uW bnqRL+e0VXV4rUbuqDZRm3fWwnTe6WmM/b2dAy5z5xfleH8QuVdaERmlhsEj3dGXZtaK OKd7LrdfOUnM2XCOCS1EXpA5DOWGyJm2gjUXk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=N67Zp1XY4qKa3NxJa5bBoyNpr/K4YmTSy5pefYnl2/g=; b=gxqnDIUmaHcc0rKLsTX/7wjR46S4dSs6h1Y4wkI++jV74DgjBhzCWH+kiYYBBxv3T1 73RkyK2jrCdxYaKM/fnR2w9C7pI5IK1KM/S1Oemwa9JTVoRNLWmcdfn7SSMa2TeUIGKV TiWzB3z1Ru9xyNabeK72E+YD/S9Ewl9Yog2cRgaDakDr2oXMYKrdXifaG7gidzQdsvXc p3Ar3j/ulsc3YcRyyCZyGnNs8Icy/TV7+U7MdpT3VdjuMtXWu69uWrLgqBbOHez+NI2J TrWfYD1zhSZrO/ZvYvORCqkUUyhfElQEfPTG+bcLMUYn07zjqUNdh64kDSJKRXoYTu57 pouQ== X-Gm-Message-State: AODbwcCePxsVgXb0wlprl/FJ4rX/OrkFDj9efLPD4V4jDRTitc3wCjBT d69BaCq/ykQFJDqp X-Received: by 10.84.179.99 with SMTP id a90mr13779340plc.26.1494921266183; Tue, 16 May 2017 00:54:26 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id 3sm22566370pfp.11.2017.05.16.00.54.23 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 May 2017 00:54:25 -0700 (PDT) From: Baolin Wang X-Google-Original-From: Baolin Wang To: ohad@wizery.com, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, broonie@kernel.org, baolin.wang@linaro.org, baolin.wang@spreadtrum.com Subject: [PATCH] hwspinlock: sprd: Add hardware spinlock driver Date: Tue, 16 May 2017 15:54:01 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Spreadtrum hardware spinlock device can provide hardware assistance for synchronization between the multiple subsystems. Signed-off-by: Baolin Wang --- drivers/hwspinlock/Kconfig | 9 ++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/sprd_hwspinlock.c | 243 ++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 drivers/hwspinlock/sprd_hwspinlock.c -- 1.7.9.5 diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index 73a4016..25304e0 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -53,4 +53,13 @@ config HSEM_U8500 If unsure, say N. +config HWSPINLOCK_SPRD + tristate "SPRD Hardware Spinlock device" + depends on ARCH_SPRD + select HWSPINLOCK + help + Say y here to support the SPRD Hardware Spinlock device. + + If unsure, say N. + endmenu diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index 6b59cb5a..03c442f 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SIRF) += sirf_hwspinlock.o obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o +obj-$(CONFIG_HWSPINLOCK_SPRD) += sprd_hwspinlock.o diff --git a/drivers/hwspinlock/sprd_hwspinlock.c b/drivers/hwspinlock/sprd_hwspinlock.c new file mode 100644 index 0000000..898738f --- /dev/null +++ b/drivers/hwspinlock/sprd_hwspinlock.c @@ -0,0 +1,243 @@ +/* + * Spreadtrum hardware spinlock driver + * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hwspinlock_internal.h" + +/* hwspinlock registers definition */ +#define HWSPINLOCK_RECCTRL 0x4 +#define HWSPINLOCK_TTLSTS 0x8 +#define HWSPINLOCK_FLAG0 0x10 +#define HWSPINLOCK_FLAG1 0x14 +#define HWSPINLOCK_FLAG2 0x18 +#define HWSPINLOCK_FLAG3 0x1c +#define HWSPINLOCK_MASTERID(_X_) (0x80 + 0x4 * (_X_)) +#define HWSPINLOCK_TOKEN(_X_) (0x800 + 0x4 * (_X_)) +#define HWSPINLOCK_VERID 0xFFC + +/* untoken lock value */ +#define HWSPINLOCK_NOTTAKEN 0x55aa10c5 +/* bits definition of RECCTRL reg */ +#define HWSPINLOCK_ID 0x0 +#define HWSPINLOCK_USER_BITS 0x1 + +/* hwspinlock number */ +#define SPRD_HWLOCKS_NUM 32 + +struct sprd_hwspinlock_dev { + void __iomem *base; + struct clk *clk; + unsigned char status[SPRD_HWLOCKS_NUM]; + struct hwspinlock_device bank; +}; + +static const struct of_device_id sprd_hwspinlock_of_match[] = { + { .compatible = "sprd,hwspinlock-r3p0",}, + { /* sentinel */ } +}; + +static struct sprd_hwspinlock_dev *sprd_lock_to_dev(struct hwspinlock *lock) +{ + struct hwspinlock_device *hwbank; + unsigned int lock_id = hwlock_to_id(lock); + + hwbank = container_of(lock, struct hwspinlock_device, lock[lock_id]); + return container_of(hwbank, struct sprd_hwspinlock_dev, bank); +} + +/* set the hardware spinlock record type */ +static void sprd_set_hwspinlock_record(struct sprd_hwspinlock_dev *sprd_hwlock, + unsigned int type) +{ + writel_relaxed(type, sprd_hwlock->base + HWSPINLOCK_RECCTRL); +} + +/* get the hardware spinlock master/user id */ +static unsigned int sprd_get_hwspinlock_id(struct sprd_hwspinlock_dev *sprd_hwlock, + unsigned int lock_id) +{ + return readl_relaxed(sprd_hwlock->base + HWSPINLOCK_MASTERID(lock_id)); +} + +/* record the hardware spinlock status */ +static int sprd_record_hwspinlock_sts(struct hwspinlock *lock) +{ + struct sprd_hwspinlock_dev *sprd_hwlock = sprd_lock_to_dev(lock); + unsigned int lock_id = hwlock_to_id(lock); + unsigned char status; + + if (lock_id >= SPRD_HWLOCKS_NUM) { + dev_err(sprd_hwlock->bank.dev, "lock id is out of the range\n"); + return -ENXIO; + } + + /* get the hardware spinlock status */ + status = !!(readl_relaxed(sprd_hwlock->base + HWSPINLOCK_TTLSTS) & + BIT(lock_id)); + + sprd_hwlock->status[lock_id] = status; + return 0; +} + +/* try to lock the hardware spinlock */ +static int sprd_hwspinlock_trylock(struct hwspinlock *lock) +{ + struct sprd_hwspinlock_dev *sprd_hwlock = sprd_lock_to_dev(lock); + void __iomem *addr = lock->priv; + + if (!readl_relaxed(addr)) + goto locked; + + dev_warn(sprd_hwlock->bank.dev, + "hwspinlock [%d] lock failed and master/user id = %d!\n", + hwlock_to_id(lock), + sprd_get_hwspinlock_id(sprd_hwlock, hwlock_to_id(lock))); + return 0; + +locked: + sprd_record_hwspinlock_sts(lock); + return 1; +} + +/* unlock the hardware spinlock */ +static void sprd_hwspinlock_unlock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + + writel_relaxed(HWSPINLOCK_NOTTAKEN, lock_addr); + sprd_record_hwspinlock_sts(lock); +} + +/* The specs recommended below number as the retry delay time */ +static void sprd_hwspinlock_relax(struct hwspinlock *lock) +{ + ndelay(10); +} + +static const struct hwspinlock_ops sprd_hwspinlock_ops = { + .trylock = sprd_hwspinlock_trylock, + .unlock = sprd_hwspinlock_unlock, + .relax = sprd_hwspinlock_relax, +}; + +static int sprd_hwspinlock_probe(struct platform_device *pdev) +{ + struct sprd_hwspinlock_dev *sprd_hwlock; + struct hwspinlock *lock; + struct resource *res; + int i, ret; + + if (!pdev->dev.of_node) + return -ENODEV; + + sprd_hwlock = devm_kzalloc(&pdev->dev, + sizeof(struct sprd_hwspinlock_dev) + + SPRD_HWLOCKS_NUM * sizeof(*lock), + GFP_KERNEL); + if (!sprd_hwlock) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sprd_hwlock->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(sprd_hwlock->base)) + return PTR_ERR(sprd_hwlock->base); + + sprd_hwlock->clk = of_clk_get_by_name(pdev->dev.of_node, "enable"); + if (IS_ERR(sprd_hwlock->clk)) { + dev_err(&pdev->dev, "get hwspinlock clock failed!\n"); + return PTR_ERR(sprd_hwlock->clk); + } + + clk_prepare_enable(sprd_hwlock->clk); + + /* set the hwspinlock to record user id to identify subsystems */ + sprd_set_hwspinlock_record(sprd_hwlock, HWSPINLOCK_USER_BITS); + + for (i = 0; i < SPRD_HWLOCKS_NUM; i++) { + lock = &sprd_hwlock->bank.lock[i]; + lock->priv = sprd_hwlock->base + HWSPINLOCK_TOKEN(i); + } + + platform_set_drvdata(pdev, sprd_hwlock); + pm_runtime_enable(&pdev->dev); + + ret = hwspin_lock_register(&sprd_hwlock->bank, &pdev->dev, + &sprd_hwspinlock_ops, 0, SPRD_HWLOCKS_NUM); + if (ret) { + dev_err(&pdev->dev, "hwspinlock register failed!\n"); + pm_runtime_disable(&pdev->dev); + clk_disable_unprepare(sprd_hwlock->clk); + return ret; + } + + return 0; +} + +static int sprd_hwspinlock_remove(struct platform_device *pdev) +{ + struct sprd_hwspinlock_dev *sprd_hwlock = platform_get_drvdata(pdev); + int ret; + + ret = hwspin_lock_unregister(&sprd_hwlock->bank); + if (ret) { + dev_err(&pdev->dev, "hwspinlock unregister failed: %d\n", ret); + return ret; + } + + pm_runtime_disable(&pdev->dev); + clk_disable_unprepare(sprd_hwlock->clk); + return 0; +} + +static struct platform_driver sprd_hwspinlock_driver = { + .probe = sprd_hwspinlock_probe, + .remove = sprd_hwspinlock_remove, + .driver = { + .name = "sprd_hwspinlock", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(sprd_hwspinlock_of_match), + }, +}; + +static int __init sprd_hwspinlock_init(void) +{ + return platform_driver_register(&sprd_hwspinlock_driver); +} +postcore_initcall(sprd_hwspinlock_init); + +static void __exit sprd_hwspinlock_exit(void) +{ + platform_driver_unregister(&sprd_hwspinlock_driver); +} +module_exit(sprd_hwspinlock_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver for Spreadtrum"); +MODULE_AUTHOR("Baolin Wang "); +MODULE_AUTHOR("Lanqing Liu "); +MODULE_AUTHOR("Long Cheng ");