[0/2] net: Add LiteETH network driver

This adds a driver for the LiteX network device, LiteETH.

It is a simple driver for the FPGA based Ethernet device used in various
RISC-V, PowerPC's microwatt, OpenRISC's mor1k and other FPGA based
systems on chip.

Joel Stanley (2):
  dt-bindings: net: Add bindings for LiteETH
  net: Add driver for LiteX's LiteETH network interface

 .../bindings/net/litex,liteeth.yaml           |  62 ++++
 drivers/net/ethernet/Kconfig                  |   1 +
 drivers/net/ethernet/Makefile                 |   1 +
 drivers/net/ethernet/litex/Kconfig            |  24 ++
 drivers/net/ethernet/litex/Makefile           |   5 +
 drivers/net/ethernet/litex/litex_liteeth.c    | 340 ++++++++++++++++++
 6 files changed, 433 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml
 create mode 100644 drivers/net/ethernet/litex/Kconfig
 create mode 100644 drivers/net/ethernet/litex/Makefile
 create mode 100644 drivers/net/ethernet/litex/litex_liteeth.c

On Fri, Aug 06, 2021 at 03:19:03PM +0930, Joel Stanley wrote:
> LiteETH is a small footprint and configurable Ethernet core for FPGA
> based system on chips.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
>  .../bindings/net/litex,liteeth.yaml           | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
> new file mode 100644
> index 000000000000..e2a837dbfdaa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/litex,liteeth.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LiteX LiteETH ethernet device
> +
> +maintainers:
> +  - Joel Stanley <joel@jms.id.au>
> +
> +description: |
> +  LiteETH is a small footprint and configurable Ethernet core for FPGA based
> +  system on chips.
> +
> +  The hardware source is Open Source and can be found on at
> +  https://github.com/enjoy-digital/liteeth/.
> +
> +properties:
> +  compatible:
> +    const: litex,liteeth
> +
> +  reg:
> +    minItems: 3
> +    items:
> +      - description: MAC registers
> +      - description: MDIO registers
> +      - description: Packet buffer

Hi Joel

How configurable is the synthesis? Can the MDIO bus be left out? You
can have only the MDIO bus and no MAC?

I've not looked at the driver yet, but if the MDIO bus has its own
address space, you could consider making it a standalone
device. Somebody including two or more LiteETH blocks could then have
one shared MDIO bus. That is a supported Linux architecture.

> +
> +  interrupts:
> +    maxItems: 1
> +
> +  rx-fifo-depth:
> +    description: Receive FIFO size, in units of 2048 bytes
> +
> +  tx-fifo-depth:
> +    description: Transmit FIFO size, in units of 2048 bytes
> +
> +  mac-address:
> +    description: MAC address to use
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    mac: ethernet@8020000 {
> +        compatible = "litex,liteeth";
> +        reg = <0x8021000 0x100
> +               0x8020800 0x100
> +               0x8030000 0x2000>;
> +        rx-fifo-depth = <2>;
> +        tx-fifo-depth = <2>;
> +        interrupts = <0x11 0x1>;
> +    };

You would normally expect to see some MDIO properties here, a link to
the standard MDIO yaml, etc.

    Andrew

On Sat, 7 Aug 2021 at 19:05, Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Fri, Aug 06, 2021 at 03:19:03PM +0930, Joel Stanley wrote:
> > LiteETH is a small footprint and configurable Ethernet core for FPGA
> > based system on chips.
> >
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > ---
> >  .../bindings/net/litex,liteeth.yaml           | 62 +++++++++++++++++++
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
> > new file mode 100644
> > index 000000000000..e2a837dbfdaa
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
> > @@ -0,0 +1,62 @@
> > +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/litex,liteeth.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: LiteX LiteETH ethernet device
> > +
> > +maintainers:
> > +  - Joel Stanley <joel@jms.id.au>
> > +
> > +description: |
> > +  LiteETH is a small footprint and configurable Ethernet core for FPGA based
> > +  system on chips.
> > +
> > +  The hardware source is Open Source and can be found on at
> > +  https://github.com/enjoy-digital/liteeth/.
> > +
> > +properties:
> > +  compatible:
> > +    const: litex,liteeth
> > +
> > +  reg:
> > +    minItems: 3
> > +    items:
> > +      - description: MAC registers
> > +      - description: MDIO registers
> > +      - description: Packet buffer
>
> Hi Joel
>
> How configurable is the synthesis? Can the MDIO bus be left out? You
> can have only the MDIO bus and no MAC?
>
> I've not looked at the driver yet, but if the MDIO bus has its own
> address space, you could consider making it a standalone
> device. Somebody including two or more LiteETH blocks could then have
> one shared MDIO bus. That is a supported Linux architecture.

It's currently integrated as one device. If you instatined two blocks,
you would end up with two mdio controllers, each inside those two
liteeth blocks.

Obviously being software someone could change that. We've had a few
discussions about the infinite possibilities of a soft SoC and what
that means for adding driver support to mainline. I think having some
basic driver support is useful, particularly as we then get close
review as Jakub provided.

The liteeth block has seen a lot of use under Linux by risc-v
(vexriscv), powerpc (microwatt), and openrisc (mor1k) designs. The
microwatt and or1k designs have mainline support, making them easy to
test. This driver will support the normal configurations of those
platforms.

As the soft core project evolves, we can revisit what goes in
mainline, how flexible that driver support needs to be, and how best
to manage that.

>
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  rx-fifo-depth:
> > +    description: Receive FIFO size, in units of 2048 bytes
> > +
> > +  tx-fifo-depth:
> > +    description: Transmit FIFO size, in units of 2048 bytes
> > +
> > +  mac-address:
> > +    description: MAC address to use
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    mac: ethernet@8020000 {
> > +        compatible = "litex,liteeth";
> > +        reg = <0x8021000 0x100
> > +               0x8020800 0x100
> > +               0x8030000 0x2000>;
> > +        rx-fifo-depth = <2>;
> > +        tx-fifo-depth = <2>;
> > +        interrupts = <0x11 0x1>;
> > +    };
>
> You would normally expect to see some MDIO properties here, a link to
> the standard MDIO yaml, etc.

Do you have a favourite example that I could follow?

> > Hi Joel
> >
> > How configurable is the synthesis? Can the MDIO bus be left out? You
> > can have only the MDIO bus and no MAC?
> >
> > I've not looked at the driver yet, but if the MDIO bus has its own
> > address space, you could consider making it a standalone
> > device. Somebody including two or more LiteETH blocks could then have
> > one shared MDIO bus. That is a supported Linux architecture.
> 
> It's currently integrated as one device. If you instatined two blocks,
> you would end up with two mdio controllers, each inside those two
> liteeth blocks.

O.K. So at the moment, that is the default architecture, and the
driver should then support it. But since there appears to be a clean
address space split, the Linux MDIO driver could still be
separate. But it might depend on the reset, since the register is in
the MDIO address space. So again, we need to understand what that
reset is about.

> Obviously being software someone could change that. We've had a few
> discussions about the infinite possibilities of a soft SoC and what
> that means for adding driver support to mainline.

Has any thought been given to making the hardware somehow
enumerable/self describing? A register containing features which have
been synthesised? There could be a bit indicating is the MDIO bus
master is present, etc.

> As the soft core project evolves, we can revisit what goes in
> mainline, how flexible that driver support needs to be, and how best
> to manage that.

We can do that, but we have to keep backwards compatibility in
mind. We cannot break older synthesised IP blobs because a new feature
has come along and the driver has changed. It is best to put some
thought into that now, how forward/backward compatibility will work.
A revision register, a self description register, something which
helps the software driver identify what the 'hardware' is.

      Andrew

> 
> >
> > > +
> > > +  interrupts:
> > > +    maxItems: 1
> > > +
> > > +  rx-fifo-depth:
> > > +    description: Receive FIFO size, in units of 2048 bytes
> > > +
> > > +  tx-fifo-depth:
> > > +    description: Transmit FIFO size, in units of 2048 bytes
> > > +
> > > +  mac-address:
> > > +    description: MAC address to use
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - interrupts
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    mac: ethernet@8020000 {
> > > +        compatible = "litex,liteeth";
> > > +        reg = <0x8021000 0x100
> > > +               0x8020800 0x100
> > > +               0x8030000 0x2000>;
> > > +        rx-fifo-depth = <2>;
> > > +        tx-fifo-depth = <2>;
> > > +        interrupts = <0x11 0x1>;
> > > +    };
> >
> > You would normally expect to see some MDIO properties here, a link to
> > the standard MDIO yaml, etc.
> 
> Do you have a favourite example that I could follow?

Documentation/devicetree/bindings/net/mdio.yaml describes all the
standard properties. Picking a file at random:

Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml