From patchwork Thu Jul 15 07:45:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 477874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E987CC47E4B for ; Thu, 15 Jul 2021 07:48:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCEC861370 for ; Thu, 15 Jul 2021 07:48:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240568AbhGOHvm (ORCPT ); Thu, 15 Jul 2021 03:51:42 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7016 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240496AbhGOHvf (ORCPT ); Thu, 15 Jul 2021 03:51:35 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4GQRDj474hzXtLW; Thu, 15 Jul 2021 15:43:01 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Thu, 15 Jul 2021 15:48:40 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 15 Jul 2021 15:48:40 +0800 From: Guangbin Huang To: , , CC: , , , , Subject: [PATCH V2 net-next 9/9] net: hns3: add support for VF setting rx/tx buffer size by devlink param Date: Thu, 15 Jul 2021 15:45:10 +0800 Message-ID: <1626335110-50769-10-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1626335110-50769-1-git-send-email-huangguangbin2@huawei.com> References: <1626335110-50769-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Hao Chen Add support for VF setting rx/tx buffer size by devlink param Signed-off-by: Hao Chen Signed-off-by: Guangbin Huang --- .../hisilicon/hns3/hns3vf/hclgevf_devlink.c | 88 +++++++++++++++++++++- .../hisilicon/hns3/hns3vf/hclgevf_devlink.h | 7 ++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 3 + 3 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c index bce598913dc3..4c364055e464 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c @@ -34,6 +34,37 @@ static int hclgevf_devlink_info_get(struct devlink *devlink, version_str); } +static void hclgevf_devlink_get_param_setting(struct devlink *devlink) +{ + struct hclgevf_devlink_priv *priv = devlink_priv(devlink); + struct hclgevf_dev *hdev = priv->hdev; + struct pci_dev *pdev = hdev->pdev; + union devlink_param_value val; + int i, ret; + + ret = devlink_param_driverinit_value_get(devlink, + HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + &val); + if (!ret) { + hdev->rx_buf_len = val.vu32; + hdev->nic.kinfo.rx_buf_len = hdev->rx_buf_len; + for (i = 0; i < hdev->num_tqps; i++) + hdev->htqp[i].q.buf_size = hdev->rx_buf_len; + } else { + dev_err(&pdev->dev, + "failed to get rx buffer size, ret = %d\n", ret); + } + + ret = devlink_param_driverinit_value_get(devlink, + HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, + &val); + if (!ret) + hdev->nic.kinfo.devlink_tx_spare_buf_size = val.vu32; + else + dev_err(&pdev->dev, + "failed to get tx buffer size, ret = %d\n", ret); +} + static int hclgevf_devlink_reload_down(struct devlink *devlink, bool netns_change, enum devlink_reload_action action, @@ -106,6 +137,49 @@ static const struct devlink_ops hclgevf_devlink_ops = { .reload_up = hclgevf_devlink_reload_up, }; +static int +hclgevf_devlink_rx_buffer_size_validate(struct devlink *devlink, u32 id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ +#define HCLGEVF_RX_BUF_LEN_2K 2048 +#define HCLGEVF_RX_BUF_LEN_4K 4096 + + if (val.vu32 != HCLGEVF_RX_BUF_LEN_2K && + val.vu32 != HCLGEVF_RX_BUF_LEN_4K) { + NL_SET_ERR_MSG_MOD(extack, "Supported size is 2048 or 4096"); + return -EOPNOTSUPP; + } + + return 0; +} + +static const struct devlink_param hclgevf_devlink_params[] = { + DEVLINK_PARAM_DRIVER(HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + "rx_buffer_len", DEVLINK_PARAM_TYPE_U32, + BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), + NULL, NULL, + hclgevf_devlink_rx_buffer_size_validate), + DEVLINK_PARAM_DRIVER(HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, + "tx_buffer_size", DEVLINK_PARAM_TYPE_U32, + BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), + NULL, NULL, NULL), +}; + +void hclgevf_devlink_set_params_init_values(struct hclgevf_dev *hdev) +{ + union devlink_param_value value; + + value.vu32 = hdev->rx_buf_len; + devlink_param_driverinit_value_set(hdev->devlink, + HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + value); + value.vu32 = 0; + devlink_param_driverinit_value_set(hdev->devlink, + HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, + value); +} + int hclgevf_devlink_init(struct hclgevf_dev *hdev) { struct pci_dev *pdev = hdev->pdev; @@ -130,10 +204,20 @@ int hclgevf_devlink_init(struct hclgevf_dev *hdev) hdev->devlink = devlink; + ret = devlink_params_register(devlink, hclgevf_devlink_params, + ARRAY_SIZE(hclgevf_devlink_params)); + if (ret) { + dev_err(&pdev->dev, + "failed to register devlink params, ret = %d\n", ret); + goto out_param_reg_fail; + } + devlink_reload_enable(devlink); return 0; - +out_param_reg_fail: + hdev->devlink = NULL; + devlink_unregister(devlink); out_reg_fail: devlink_free(devlink); return ret; @@ -148,6 +232,8 @@ void hclgevf_devlink_uninit(struct hclgevf_dev *hdev) devlink_reload_disable(devlink); + devlink_params_unregister(devlink, hclgevf_devlink_params, + ARRAY_SIZE(hclgevf_devlink_params)); devlink_unregister(devlink); devlink_free(devlink); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h index e09ea3d8a963..2159ec4a3523 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h @@ -6,10 +6,17 @@ #include "hclgevf_main.h" +enum hclgevf_devlink_param_id { + HCLGEVF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, +}; + struct hclgevf_devlink_priv { struct hclgevf_dev *hdev; }; +void hclgevf_devlink_set_params_init_values(struct hclgevf_dev *hdev); int hclgevf_devlink_init(struct hclgevf_dev *hdev); void hclgevf_devlink_uninit(struct hclgevf_dev *hdev); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c index 1e03c4d16125..ce7d652594e1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c @@ -3374,6 +3374,9 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) goto err_config; } + hclgevf_devlink_set_params_init_values(hdev); + devlink_params_publish(hdev->devlink); + ret = hclgevf_alloc_tqps(hdev); if (ret) { dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);