From patchwork Tue Oct 3 15:53:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 114700 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2033478qgn; Tue, 3 Oct 2017 08:53:34 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCJDVuBOFxzn7SJ2shLzZH+FsdL2VnhQpOntkDlRzc0AeiFRHfmfa1W9AlVeSM4QMCQW2R5 X-Received: by 10.99.50.70 with SMTP id y67mr15443602pgy.291.1507046014483; Tue, 03 Oct 2017 08:53:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507046014; cv=none; d=google.com; s=arc-20160816; b=mikfVO3OfNH/T96KTPlLLfbBtlB249ipmXAOEHvM0XopUNHn7k4Yx9ASJJW2TBROex Wj63P6rcHARrOMgbZn4ryRX/PfcUEnAqXdMVoeiuwGMtE12X3XcRDGLGjaNLrNUne+Zu h+YDjCjJcGGP04zGl4CsumxJT//GhQ8fK/9EUOUdnu95JZp7Mw95gvJ1fSi9fdfkrAod 4fKkIXu5R/fBIi/h3YOOMUe1u45FrCcrFjUQTdvYQMPdxrq+sy7JfIvjLKLMuAQ+EHw8 EOsd4DBiFnbcZI+dYWPaBD4A0ag2hAwkIOoCg4CR1zUkK+Bel4NRt/q7doT50p1hv6Xb NyLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature:arc-authentication-results; bh=hz35wv1djZnSYDGYDPeqhV3wSi/gwSw+0Iu9AqHfWzM=; b=MBzhh4zjZEjXZ3gkjwp1zCxA+NTZ8e4DQhwCIRH6KMHG9B3YQ8adMMJHpdUA2Zyvw9 h6eVeDyJkXb4oBmaHQUQUkIRlPMq3GxOQKX7JXUlbW+57fOhxFhRdmjimPZ8N/3XkwNX VNSBXrQ72KbtETExBlhPjlZhXhj1hDLa5hniSbM3lLp06hkS4tsJ3xpFmdYzG2vWe+8r GGQJrX/rLxhuYDTQdEwEt4TSPu+LVYJkZ8LdskUVDg2G8Y/BxaislcD/12/KbQTys0jS tgSJAfBbQQaqdtAwBtTSbpEsdSXHLNWpj8vp5ltRRbZL6JlLLeMomKEbo1lAEoc849o4 bmPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lk5DfSdg; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e73si2958249pfb.421.2017.10.03.08.53.34; Tue, 03 Oct 2017 08:53:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lk5DfSdg; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752427AbdJCPxb (ORCPT + 8 others); Tue, 3 Oct 2017 11:53:31 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:49336 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751201AbdJCPxa (ORCPT ); Tue, 3 Oct 2017 11:53:30 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v93FrK8b012173; Tue, 3 Oct 2017 10:53:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507046000; bh=dZ3wpx8x4/mRfk2Z/4zDEt68iiJw9rD4xUL3KVBYjBQ=; h=From:To:CC:Subject:Date; b=lk5DfSdgV3mKoXGuyqzy/ddyC8EjuYrqalZ7HBMwM4Wo0Ae3xH/iJHIpQ70nELS1J KQNDyXfkPBHPeiVprpyQh10VYlm4nMWR1RYXx9/QiaNjent5CypSAAA4H6AzhI95lz OnFCmGJ2PkuTXvb2jtnZv9NYfgXwFQCiKRobnPbs= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v93FrKFu017525; Tue, 3 Oct 2017 10:53:20 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 3 Oct 2017 10:53:20 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 3 Oct 2017 10:53:20 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v93FrKVq027700; Tue, 3 Oct 2017 10:53:20 -0500 Received: from localhost ([172.22.136.251]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v93FrK308847; Tue, 3 Oct 2017 10:53:20 -0500 (CDT) From: Dan Murphy To: , CC: , Dan Murphy Subject: [PATCH] net: phy: DP83822 initial driver submission Date: Tue, 3 Oct 2017 10:53:16 -0500 Message-ID: <20171003155316.12312-1-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for the TI DP83822 10/100Mbit ethernet phy. The DP83822 provides flexibility to connect to a MAC through a standard MII, RMII or RGMII interface. Datasheet: http://www.ti.com/product/DP83822I/datasheet Signed-off-by: Dan Murphy --- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83822.c | 313 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/net/phy/dp83822.c -- 1.9.1 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index cd931cf..8e78a48 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -277,6 +277,11 @@ config DAVICOM_PHY ---help--- Currently supports dm9161e and dm9131 +config DP83822_PHY + tristate "Texas Instruments DP83822 PHY" + ---help--- + Supports the DP83822 PHY. + config DP83848_PHY tristate "Texas Instruments DP83848 PHY" ---help--- diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 416df92..df3b82b 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CICADA_PHY) += cicada.o obj-$(CONFIG_CORTINA_PHY) += cortina.o obj-$(CONFIG_DAVICOM_PHY) += davicom.o obj-$(CONFIG_DP83640_PHY) += dp83640.o +obj-$(CONFIG_DP83822_PHY) += dp83822.o obj-$(CONFIG_DP83848_PHY) += dp83848.o obj-$(CONFIG_DP83867_PHY) += dp83867.o obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c new file mode 100644 index 0000000..1d77515 --- /dev/null +++ b/drivers/net/phy/dp83822.c @@ -0,0 +1,313 @@ +/* + * Driver for the Texas Instruments DP83822 PHY + * + * Copyright (C) 2017 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DP83822_PHY_ID 0x2000a240 +#define DP83822_DEVADDR 0x1f + +#define MII_DP83822_MISR1 0x12 +#define MII_DP83822_MISR2 0x13 +#define MII_DP83822_RESET_CTRL 0x1f + +#define DP83822_HW_RESET BIT(15) +#define DP83822_SW_RESET BIT(14) + +/* MISR1 bits */ +#define DP83822_RX_ERR_HF_INT_EN BIT(0) +#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) +#define DP83822_ANEG_COMPLETE_INT_EN BIT(2) +#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) +#define DP83822_SPEED_CHANGED_INT_EN BIT(4) +#define DP83822_LINK_STAT_INT_EN BIT(5) +#define DP83822_ENERGY_DET_INT_EN BIT(6) +#define DP83822_LINK_QUAL_INT_EN BIT(7) + +/* MISR2 bits */ +#define DP83822_JABBER_DET_INT_EN BIT(0) +#define DP83822_WOL_PKT_INT_EN BIT(1) +#define DP83822_SLEEP_MODE_INT_EN BIT(2) +#define DP83822_MDI_XOVER_INT_EN BIT(3) +#define DP83822_LB_FIFO_INT_EN BIT(4) +#define DP83822_PAGE_RX_INT_EN BIT(5) +#define DP83822_ANEG_ERR_INT_EN BIT(6) +#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) + +/* INT_STAT1 bits */ +#define DP83822_WOL_INT_EN BIT(4) +#define DP83822_WOL_INT_STAT BIT(12) + +#define MII_DP83822_RXSOP1 0x04A5 +#define MII_DP83822_RXSOP2 0x04A6 +#define MII_DP83822_RXSOP3 0x04A7 + +/* WoL Registers */ +#define MII_DP83822_WOL_CFG 0x04A0 +#define MII_DP83822_WOL_STAT 0x04A1 +#define MII_DP83822_WOL_DA1 0x04A2 +#define MII_DP83822_WOL_DA2 0x04A3 +#define MII_DP83822_WOL_DA3 0x04A4 + +/* WoL bits */ +#define DP83822_WOL_MAGIC_EN BIT(1) +#define DP83822_WOL_SECURE_ON BIT(5) +#define DP83822_WOL_EN BIT(7) +#define DP83822_WOL_INDICATION_SEL BIT(8) +#define DP83822_WOL_CLR_INDICATION BIT(11) + +static int dp83822_ack_interrupt(struct phy_device *phydev) +{ + int err = phy_read(phydev, MII_DP83822_MISR1); + + if (err < 0) + return err; + + err = phy_read(phydev, MII_DP83822_MISR2); + if (err < 0) + return err; + + return 0; +} + +static int dp83822_set_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + struct net_device *ndev = phydev->attached_dev; + u16 value; + const u8 *mac; + + if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { + mac = (const u8 *)ndev->dev_addr; + + if (!is_valid_ether_addr(mac)) + return -EFAULT; + + /* MAC addresses start with byte 5, but stored in mac[0]. + * 822 PHYs store bytes 4|5, 2|3, 0|1 + */ + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_DA1, (mac[1] << 8) | mac[0]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_DA2, (mac[3] << 8) | mac[2]); + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, + (mac[5] << 8) | mac[4]); + + value = phy_read_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_CFG); + if (wol->wolopts & WAKE_MAGIC) + value |= DP83822_WOL_MAGIC_EN; + else + value &= ~DP83822_WOL_MAGIC_EN; + + if (wol->wolopts & WAKE_MAGICSECURE) { + value |= DP83822_WOL_SECURE_ON; + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP1, + (wol->sopass[1] << 8) | wol->sopass[0]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP2, + (wol->sopass[3] << 8) | wol->sopass[2]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP3, + (wol->sopass[5] << 8) | wol->sopass[4]); + } else { + value &= ~DP83822_WOL_SECURE_ON; + } + + value |= (DP83822_WOL_EN | DP83822_WOL_CLR_INDICATION | + DP83822_WOL_CLR_INDICATION); + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, + value); + } else { + value = + phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + value &= (~DP83822_WOL_EN); + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, + value); + } + + return 0; +} + +static void dp83822_get_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + int value; + + wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); + wol->wolopts = 0; + + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + if (value & DP83822_WOL_MAGIC_EN) + wol->wolopts |= WAKE_MAGIC; + + if (value & DP83822_WOL_SECURE_ON) + wol->wolopts |= WAKE_MAGICSECURE; + + if (~value & DP83822_WOL_CLR_INDICATION) + wol->wolopts = 0; + + wol->sopass[0] = (phy_read_mmd(phydev, + DP83822_DEVADDR, + MII_DP83822_RXSOP1) & 0xFF); + wol->sopass[1] = + (phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP1) >> 8); + wol->sopass[2] = + (phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP2) & 0xFF); + wol->sopass[3] = + (phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP2) >> 8); + wol->sopass[4] = + (phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP3) & 0xFF); + wol->sopass[5] = + (phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP3) >> 8); +} + +static int dp83822_config_intr(struct phy_device *phydev) +{ + int misr_status; + int err; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { + misr_status = phy_read(phydev, MII_DP83822_MISR1); + if (misr_status < 0) + return misr_status; + + misr_status |= (DP83822_RX_ERR_HF_INT_EN | + DP83822_FALSE_CARRIER_HF_INT_EN | + DP83822_ANEG_COMPLETE_INT_EN | + DP83822_DUP_MODE_CHANGE_INT_EN | + DP83822_SPEED_CHANGED_INT_EN | + DP83822_LINK_STAT_INT_EN | + DP83822_ENERGY_DET_INT_EN | + DP83822_LINK_QUAL_INT_EN); + + err = phy_write(phydev, MII_DP83822_MISR1, misr_status); + if (err < 0) + return err; + + misr_status = phy_read(phydev, MII_DP83822_MISR2); + if (misr_status < 0) + return misr_status; + + misr_status |= (DP83822_JABBER_DET_INT_EN | + DP83822_WOL_PKT_INT_EN | + DP83822_SLEEP_MODE_INT_EN | + DP83822_MDI_XOVER_INT_EN | + DP83822_LB_FIFO_INT_EN | + DP83822_PAGE_RX_INT_EN | + DP83822_ANEG_ERR_INT_EN | + DP83822_EEE_ERROR_CHANGE_INT_EN); + + err = phy_write(phydev, MII_DP83822_MISR2, misr_status); + } else { + err = phy_write(phydev, MII_DP83822_MISR1, 0); + if (err < 0) + return err; + + err = phy_write(phydev, MII_DP83822_MISR1, 0); + } + + return err; +} + +static int dp83822_phy_reset(struct phy_device *phydev) +{ + int err; + + err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_HW_RESET); + if (err < 0) + return err; + + return 0; +} + +static int dp83822_suspend(struct phy_device *phydev) +{ + int value; + + mutex_lock(&phydev->lock); + + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + if (~value & DP83822_WOL_EN) { + value = phy_read(phydev, MII_BMCR); + phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); + } + + mutex_unlock(&phydev->lock); + + return 0; +} + +static int dp83822_resume(struct phy_device *phydev) +{ + int value; + + mutex_lock(&phydev->lock); + + value = phy_read(phydev, MII_BMCR); + phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); + + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | + DP83822_WOL_CLR_INDICATION); + + mutex_unlock(&phydev->lock); + + return 0; +} + +static struct phy_driver dp83822_driver[] = { + { + .phy_id = DP83822_PHY_ID, + .phy_id_mask = 0xfffffff0, + .name = "TI DP83822", + .features = PHY_BASIC_FEATURES, + .flags = PHY_HAS_INTERRUPT, + + .config_init = genphy_config_init, + .soft_reset = dp83822_phy_reset, + + .get_wol = dp83822_get_wol, + .set_wol = dp83822_set_wol, + + /* IRQ related */ + .ack_interrupt = dp83822_ack_interrupt, + .config_intr = dp83822_config_intr, + + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .suspend = dp83822_suspend, + .resume = dp83822_resume, + }, +}; +module_phy_driver(dp83822_driver); + +static struct mdio_device_id __maybe_unused dp83822_tbl[] = { + { DP83822_PHY_ID, 0xfffffff0 }, + { } +}; +MODULE_DEVICE_TABLE(mdio, dp83822_tbl); + +MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); +MODULE_AUTHOR("Dan Murphy