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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id 137sm1009039ioc.20.2020.09.28.16.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2020 16:04:54 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 05/10] net: ipa: share field mask values for GSI interrupt type Date: Mon, 28 Sep 2020 18:04:41 -0500 Message-Id: <20200928230446.20561-6-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200928230446.20561-1-elder@linaro.org> References: <20200928230446.20561-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The GSI interrupt type register and interrupt type mask register have the same field bits at the same locations. Use a common set of field masks for both registers rather than essentially duplicating them. The only place the interrupt mask register uses any of these is in gsi_irq_enable(). Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 4 ++-- drivers/net/ipa/gsi_reg.h | 17 +++++------------ 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index cb75f7d540571..745717477cad3 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -254,8 +254,8 @@ static void gsi_irq_enable(struct gsi *gsi) /* We don't use inter-EE channel or event interrupts */ val = GSI_CNTXT_TYPE_IRQ_MSK_ALL; - val &= ~MSK_INTER_EE_CH_CTRL_FMASK; - val &= ~MSK_INTER_EE_EV_CTRL_FMASK; + val &= ~INTER_EE_CH_CTRL_FMASK; + val &= ~INTER_EE_EV_CTRL_FMASK; iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET); val = GENMASK(gsi->channel_count - 1, 0); diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index acc9e744c67d1..598db57a68dfb 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -258,6 +258,11 @@ GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ (0x0001f080 + 0x4000 * (ee)) +#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ + GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) +#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ + (0x0001f088 + 0x4000 * (ee)) +/* The masks below are used for the TYPE_IRQ and TYPE_IRQ_MASK registers */ #define CH_CTRL_FMASK GENMASK(0, 0) #define EV_CTRL_FMASK GENMASK(1, 1) #define GLOB_EE_FMASK GENMASK(2, 2) @@ -265,18 +270,6 @@ #define INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) #define INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) #define GENERAL_FMASK GENMASK(6, 6) - -#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ - GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ - (0x0001f088 + 0x4000 * (ee)) -#define MSK_CH_CTRL_FMASK GENMASK(0, 0) -#define MSK_EV_CTRL_FMASK GENMASK(1, 1) -#define MSK_GLOB_EE_FMASK GENMASK(2, 2) -#define MSK_IEOB_FMASK GENMASK(3, 3) -#define MSK_INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) -#define MSK_INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) -#define MSK_GENERAL_FMASK GENMASK(6, 6) #define GSI_CNTXT_TYPE_IRQ_MSK_ALL GENMASK(6, 0) #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \