@@ -14,6 +14,7 @@ static const struct ipa_qsb_data ipa_qsb_data[] = {
[IPA_QSB_MASTER_DDR] = {
.max_writes = 8,
.max_reads = 12,
+ /* no outstanding read byte (beat) limit */
},
};
@@ -59,10 +59,12 @@ enum ipa_qsb_master_id {
* struct ipa_qsb_data - Qualcomm System Bus configuration data
* @max_writes: Maximum outstanding write requests for this master
* @max_reads: Maximum outstanding read requests for this master
+ * @max_reads_beats: Max outstanding read bytes in 8-byte "beats" (if non-zero)
*/
struct ipa_qsb_data {
u8 max_writes;
u8 max_reads;
+ u8 max_reads_beats; /* Not present for IPA v3.5.1 */
};
/**
@@ -274,10 +274,16 @@ ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data)
/* Max outstanding read accesses for QSB masters */
val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK);
- /* GEN_QMB_0_MAX_READS_BEATS is 0 (IPA v4.0 and above) */
- if (data->qsb_count > 1)
+ if (ipa->version >= IPA_VERSION_4_0)
+ val |= u32_encode_bits(data0->max_reads_beats,
+ GEN_QMB_0_MAX_READS_BEATS_FMASK);
+ if (data->qsb_count > 1) {
val |= u32_encode_bits(data1->max_reads,
GEN_QMB_1_MAX_READS_FMASK);
+ if (ipa->version >= IPA_VERSION_4_0)
+ val |= u32_encode_bits(data1->max_reads_beats,
+ GEN_QMB_1_MAX_READS_BEATS_FMASK);
+ }
iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET);
}
Starting with IPA v4.0, a limit is placed on the number of bytes outstanding in a transaction, to reduce latency. The limit is imposed only if this value is non-zero. We don't use a non-zero value for SC7180, but newer versions of IPA do. Prepare for that by allowing a programmed value to be specified in the platform configuration data. Signed-off-by: Alex Elder <elder@linaro.org> --- drivers/net/ipa/ipa_data-sc7180.c | 1 + drivers/net/ipa/ipa_data.h | 2 ++ drivers/net/ipa/ipa_main.c | 10 ++++++++-- 3 files changed, 11 insertions(+), 2 deletions(-) -- 2.27.0