From patchwork Tue Apr 6 10:22:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 417336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A94CC433ED for ; Tue, 6 Apr 2021 10:22:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0DC3613C4 for ; Tue, 6 Apr 2021 10:22:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241397AbhDFKWx (ORCPT ); Tue, 6 Apr 2021 06:22:53 -0400 Received: from mga09.intel.com ([134.134.136.24]:7876 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236042AbhDFKWv (ORCPT ); Tue, 6 Apr 2021 06:22:51 -0400 IronPort-SDR: nd4DcoC8MdSf1UiF3gRGrOJ5nWY8PwMnMyv+Dw+KIoS5lmAUKnaK+rDED9cGeNRnURcfKd684J NTuqVwSakeYQ== X-IronPort-AV: E=McAfee;i="6000,8403,9945"; a="193148087" X-IronPort-AV: E=Sophos;i="5.81,309,1610438400"; d="scan'208";a="193148087" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2021 03:22:42 -0700 IronPort-SDR: Ce8QKxGNyzHd2lPlXwfiSMXekdbtn8cBvZCtxDo1xUlIs0JyxUBkEIKqyZyXArDNTyhE52Y3TN FnFXKJeLrUTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,309,1610438400"; d="scan'208";a="448512067" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga002.fm.intel.com with ESMTP; 06 Apr 2021 03:22:38 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id D7376202; Tue, 6 Apr 2021 13:22:53 +0300 (EEST) From: Andy Shevchenko To: "David S. Miller" , Yangbo Lu , Vladimir Oltean , Heiko Stuebner , Andy Shevchenko , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Claudiu Manoil , Alexandre Belloni , UNGLinuxDriver@microchip.com, Jakub Kicinski , Kishon Vijay Abraham I , Vinod Koul , Andy Lutomirski , Thomas Gleixner , Vincenzo Frascino Subject: [PATCH v2 1/1] time64.h: Consolidated PSEC_PER_SEC definition Date: Tue, 6 Apr 2021 13:22:51 +0300 Message-Id: <20210406102251.60301-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org We have currently three users of the PSEC_PER_SEC each of them defining it individually. Instead, move it to time64.h to be available for everyone. There is a new user coming with the same constant in use. It will also make its life easier. Signed-off-by: Andy Shevchenko Acked-by: Heiko Stuebner --- v2: added tag (Heiko), rebased on top of newest rc Since it touches PHY stuff, I assume that the PHY tree is the best to suck this. drivers/net/ethernet/mscc/ocelot_ptp.c | 2 ++ drivers/phy/phy-core-mipi-dphy.c | 2 -- drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 8 ++++---- include/soc/mscc/ocelot_ptp.h | 2 -- include/vdso/time64.h | 1 + 5 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_ptp.c b/drivers/net/ethernet/mscc/ocelot_ptp.c index a33ab315cc6b..87ad2137ba06 100644 --- a/drivers/net/ethernet/mscc/ocelot_ptp.c +++ b/drivers/net/ethernet/mscc/ocelot_ptp.c @@ -4,6 +4,8 @@ * Copyright (c) 2017 Microsemi Corporation * Copyright 2020 NXP */ +#include + #include #include #include diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c index 14e0551cd319..77fe65367ce5 100644 --- a/drivers/phy/phy-core-mipi-dphy.c +++ b/drivers/phy/phy-core-mipi-dphy.c @@ -12,8 +12,6 @@ #include #include -#define PSEC_PER_SEC 1000000000000LL - /* * Minimum D-PHY timings based on MIPI D-PHY specification. Derived * from the valid ranges specified in Section 6.9, Table 14, Page 41 diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 8af8c6c5cc02..347dc79a18c1 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -11,16 +11,16 @@ #include #include #include +#include #include #include #include +#include #include +#include + #include #include -#include -#include - -#define PSEC_PER_SEC 1000000000000LL #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) diff --git a/include/soc/mscc/ocelot_ptp.h b/include/soc/mscc/ocelot_ptp.h index 6a7388fa7cc5..ded497d72bdb 100644 --- a/include/soc/mscc/ocelot_ptp.h +++ b/include/soc/mscc/ocelot_ptp.h @@ -37,8 +37,6 @@ enum { #define PTP_CFG_MISC_PTP_EN BIT(2) -#define PSEC_PER_SEC 1000000000000LL - #define PTP_CFG_CLK_ADJ_CFG_ENA BIT(0) #define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1) diff --git a/include/vdso/time64.h b/include/vdso/time64.h index 9d43c3f5e89d..b40cfa2aa33c 100644 --- a/include/vdso/time64.h +++ b/include/vdso/time64.h @@ -9,6 +9,7 @@ #define NSEC_PER_MSEC 1000000L #define USEC_PER_SEC 1000000L #define NSEC_PER_SEC 1000000000L +#define PSEC_PER_SEC 1000000000000LL #define FSEC_PER_SEC 1000000000000000LL #endif /* __VDSO_TIME64_H */