Series |
xen/arm: Clean-up & fixes in boot/mm code
|
expand
-
[Xen-devel,MM-PART2,v2,00/19] xen/arm: Clean-up & fixes in boot/mm code
-
[Xen-devel,MM-PART1,v3,1/8] xen/arm: Don't boot Xen on platform using AIVIVT instruction caches
-
[Xen-devel,MM-PART1,v3,2/8] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
-
[Xen-devel,MM-PART1,v3,3/8] xen/arm: Remove flush_xen_text_tlb_local()
-
[Xen-devel,MM-PART2,v2,04/19] xen/arm: Rework HSCTLR_BASE
-
[Xen-devel,MM-PART2,v2,05/19] xen/arm: Remove parameter cpuid from start_xen
-
[Xen-devel,MM-PART1,v3,6/8] xen/arm: Gather all TLB flush helpers in tlbflush.h
-
[Xen-devel,MM-PART1,v3,7/8] xen/arm: tlbflush: Rework TLB helpers
-
[Xen-devel,MM-PART1,v3,8/8] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_en...
-
[Xen-devel,MM-PART2,v2,09/19] xen/arm64: head: Correctly report the HW CPU ID
-
[Xen-devel,MM-PART2,v2,10/19] xen/arm32: head: Correctly report the HW CPU ID
-
[Xen-devel,MM-PART2,v2,11/19] xen/arm32: head: Don't set MAIR0 and MAIR1
-
[Xen-devel,MM-PART2,v2,12/19] xen/arm32: head: Always zero r3 before update a page-table entry
-
[Xen-devel,MM-PART2,v2,13/19] xen/arm32: mm: Avoid to zero and clean cache for CPU0 domheap
-
[Xen-devel,MM-PART2,v2,14/19] xen/arm32: mm: Avoid cleaning the cache for secondary CPUs page-tables
-
[Xen-devel,MM-PART2,v2,15/19] xen/arm: mm: Introduce DEFINE_PAGE_TABLE{, S} and use it
-
[Xen-devel,MM-PART2,v2,16/19] xen/arm: mm: Protect Xen page-table update with a spinlock
-
[Xen-devel,MM-PART2,v2,17/19] xen/arm: mm: Initialize page-tables earlier
-
[Xen-devel,MM-PART2,v2,18/19] xen/arm: mm: Check start is always before end in {destroy, modify}_...
-
[Xen-devel,MM-PART2,v2,19/19] xen/arm: Pair call to set_fixmap with call to clear_fixmap in copy_...
|